mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6824f127f9
System z branches have a mask to select which of the 4 CC values should cause the branch to be taken. We can invert a branch by inverting the mask. However, not all instructions can produce all 4 CC values, so inverting the branch like this can lead to some oddities. For example, integer comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater). If an integer EQ is reversed to NE before instruction selection, the branch will test for 1 or 2. If instead the branch is reversed after instruction selection (by inverting the mask), it will test for 1, 2 or 3. Both are correct, but the second isn't really canonical. This patch therefore keeps track of which CC values are possible and uses this when inverting a mask. Although this is mostly cosmestic, it fixes undefined behavior for the CIJNLH in branch-08.ll. Another fix would have been to mask out bit 0 when generating the fused compare and branch, but the point of this patch is that we shouldn't need to do that in the first place. The patch also makes it easier to reuse CC results from other instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187495 91177308-0d34-0410-b5e6-96231b3b80d8
187 lines
4.8 KiB
LLVM
187 lines
4.8 KiB
LLVM
; Test STOCs that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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declare void @foo(i32 *)
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; Test the simple case, with the loaded value first.
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define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK: clfi %r4, 42
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; CHECK: stocl %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %alt, i32 %orig
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store i32 %res, i32 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 64 bits, with the
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; loaded value first.
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define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%ext = sext i32 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK: clfi %r4, 42
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; CHECK: stocl %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%ext = sext i32 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; Test cases where the value is explicitly zero-extended to 32 bits, with the
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; loaded value first.
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define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%ext = zext i32 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK: clfi %r4, 42
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; CHECK: stocl %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%ext = zext i32 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; Check the high end of the aligned STOC range.
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define void @f7(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131071
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the next word up. Other sequences besides this one would be OK.
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define void @f8(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f8:
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; CHECK: agfi %r2, 524288
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131072
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the low end of the STOC range.
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define void @f9(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f9:
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131072
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the next word down, with the same comments as f8.
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define void @f10(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r2, -524292
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; CHECK: clfi %r4, 42
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; CHECK: stoche %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131073
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Try a frame index base.
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define void @f11(i32 %alt, i32 %limit) {
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; CHECK-LABEL: f11:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: stoche {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i32
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call void @foo(i32 *%ptr)
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%cond = icmp ult i32 %limit, 42
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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call void @foo(i32 *%ptr)
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ret void
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}
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; Test that conditionally-executed stores do not use STOC, since STOC
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; is allowed to trap even when the condition is false.
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define void @f12(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f12:
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; CHECK-NOT: stoc
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; CHECK: br %r14
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entry:
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%cmp = icmp ule i32 %a, %b
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br i1 %cmp, label %store, label %exit
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret void
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}
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