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Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163137 91177308-0d34-0410-b5e6-96231b3b80d8
424 lines
13 KiB
C++
424 lines
13 KiB
C++
//===-- HexagonMachineScheduler.h - Custom Hexagon MI scheduler. ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Custom Hexagon MI scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGONASMPRINTER_H
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#define HEXAGONASMPRINTER_H
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ResourcePriorityQueue.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/PriorityQueue.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// MachineSchedStrategy - Interface to a machine scheduling algorithm.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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class VLIWMachineScheduler;
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/// MachineSchedStrategy - Interface used by VLIWMachineScheduler to drive the selected
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/// scheduling algorithm.
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///
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/// If this works well and targets wish to reuse VLIWMachineScheduler, we may expose it
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/// in ScheduleDAGInstrs.h
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class MachineSchedStrategy {
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public:
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virtual ~MachineSchedStrategy() {}
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/// Initialize the strategy after building the DAG for a new region.
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virtual void initialize(VLIWMachineScheduler *DAG) = 0;
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/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
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/// schedule the node at the top of the unscheduled region. Otherwise it will
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/// be scheduled at the bottom.
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virtual SUnit *pickNode(bool &IsTopNode) = 0;
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/// Notify MachineSchedStrategy that VLIWMachineScheduler has scheduled a node.
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virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
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/// When all predecessor dependencies have been resolved, free this node for
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/// top-down scheduling.
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virtual void releaseTopNode(SUnit *SU) = 0;
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/// When all successor dependencies have been resolved, free this node for
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/// bottom-up scheduling.
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virtual void releaseBottomNode(SUnit *SU) = 0;
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};
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//===----------------------------------------------------------------------===//
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// ConvergingVLIWScheduler - Implementation of the standard MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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/// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
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/// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
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/// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
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class ReadyQueue {
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unsigned ID;
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std::string Name;
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std::vector<SUnit*> Queue;
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public:
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ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
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unsigned getID() const { return ID; }
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StringRef getName() const { return Name; }
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// SU is in this queue if it's NodeQueueID is a superset of this ID.
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bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
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bool empty() const { return Queue.empty(); }
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unsigned size() const { return Queue.size(); }
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typedef std::vector<SUnit*>::iterator iterator;
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iterator begin() { return Queue.begin(); }
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iterator end() { return Queue.end(); }
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iterator find(SUnit *SU) {
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return std::find(Queue.begin(), Queue.end(), SU);
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}
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void push(SUnit *SU) {
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Queue.push_back(SU);
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SU->NodeQueueId |= ID;
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}
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void remove(iterator I) {
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(*I)->NodeQueueId &= ~ID;
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*I = Queue.back();
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Queue.pop_back();
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}
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void dump() {
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dbgs() << Name << ": ";
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for (unsigned i = 0, e = Queue.size(); i < e; ++i)
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dbgs() << Queue[i]->NodeNum << " ";
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dbgs() << "\n";
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}
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};
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/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics to balance
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/// the schedule.
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class ConvergingVLIWScheduler : public MachineSchedStrategy {
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/// Store the state used by ConvergingVLIWScheduler heuristics, required for the
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/// lifetime of one invocation of pickNode().
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struct SchedCandidate {
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// The best SUnit candidate.
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SUnit *SU;
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// Register pressure values for the best candidate.
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RegPressureDelta RPDelta;
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// Best scheduling cost.
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int SCost;
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SchedCandidate(): SU(NULL), SCost(0) {}
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};
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/// Represent the type of SchedCandidate found within a single queue.
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enum CandResult {
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NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
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BestCost};
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/// Each Scheduling boundary is associated with ready queues. It tracks the
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/// current cycle in whichever direction at has moved, and maintains the state
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/// of "hazards" and other interlocks at the current cycle.
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struct SchedBoundary {
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VLIWMachineScheduler *DAG;
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ReadyQueue Available;
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ReadyQueue Pending;
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bool CheckPending;
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ScheduleHazardRecognizer *HazardRec;
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unsigned CurrCycle;
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unsigned IssueCount;
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/// MinReadyCycle - Cycle of the soonest available instruction.
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unsigned MinReadyCycle;
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// Remember the greatest min operand latency.
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unsigned MaxMinLatency;
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/// Pending queues extend the ready queues with the same ID and the
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/// PendingFlag set.
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SchedBoundary(unsigned ID, const Twine &Name):
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DAG(0), Available(ID, Name+".A"),
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Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
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CheckPending(false), HazardRec(0), CurrCycle(0), IssueCount(0),
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MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
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~SchedBoundary() { delete HazardRec; }
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bool isTop() const {
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return Available.getID() == ConvergingVLIWScheduler::TopQID;
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}
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bool checkHazard(SUnit *SU);
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void releaseNode(SUnit *SU, unsigned ReadyCycle);
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void bumpCycle();
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void bumpNode(SUnit *SU);
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void releasePending();
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void removeReady(SUnit *SU);
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SUnit *pickOnlyChoice();
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};
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VLIWMachineScheduler *DAG;
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const TargetRegisterInfo *TRI;
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// State of the top and bottom scheduled instruction boundaries.
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SchedBoundary Top;
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SchedBoundary Bot;
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public:
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/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
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enum {
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TopQID = 1,
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BotQID = 2,
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LogMaxQID = 2
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};
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ConvergingVLIWScheduler():
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DAG(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
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virtual void initialize(VLIWMachineScheduler *dag);
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virtual SUnit *pickNode(bool &IsTopNode);
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virtual void schedNode(SUnit *SU, bool IsTopNode);
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virtual void releaseTopNode(SUnit *SU);
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virtual void releaseBottomNode(SUnit *SU);
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protected:
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SUnit *pickNodeBidrectional(bool &IsTopNode);
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int SchedulingCost(ReadyQueue &Q,
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SUnit *SU, SchedCandidate &Candidate,
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RegPressureDelta &Delta, bool verbose);
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CandResult pickNodeFromQueue(ReadyQueue &Q,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Candidate);
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#ifndef NDEBUG
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void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
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PressureElement P = PressureElement());
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#endif
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};
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class VLIWResourceModel {
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/// ResourcesModel - Represents VLIW state.
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/// Not limited to VLIW targets per say, but assumes
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/// definition of DFA by a target.
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DFAPacketizer *ResourcesModel;
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const InstrItineraryData *InstrItins;
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/// Local packet/bundle model. Purely
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/// internal to the MI schedulre at the time.
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std::vector<SUnit*> Packet;
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/// Total packets created.
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unsigned TotalPackets;
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public:
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VLIWResourceModel(MachineSchedContext *C, const InstrItineraryData *IID) :
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InstrItins(IID), TotalPackets(0) {
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const TargetMachine &TM = C->MF->getTarget();
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ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL);
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// This hard requirement could be relaxed, but for now do not let it proceed.
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assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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Packet.resize(InstrItins->SchedModel->IssueWidth);
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Packet.clear();
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ResourcesModel->clearResources();
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}
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~VLIWResourceModel() {
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delete ResourcesModel;
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}
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void resetPacketState() {
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Packet.clear();
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}
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void resetDFA() {
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ResourcesModel->clearResources();
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}
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bool isResourceAvailable(SUnit *SU);
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void reserveResources(SUnit *SU);
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unsigned getTotalPackets() const { return TotalPackets; }
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};
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class VLIWMachineScheduler : public ScheduleDAGInstrs {
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/// AA - AliasAnalysis for making memory reference queries.
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AliasAnalysis *AA;
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RegisterClassInfo *RegClassInfo;
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MachineSchedStrategy *SchedImpl;
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/// state separatly for top/bottom sectioins.
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VLIWResourceModel *TopResourceModel;
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VLIWResourceModel *BotResourceModel;
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MachineBasicBlock::iterator LiveRegionEnd;
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/// Register pressure in this region computed by buildSchedGraph.
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IntervalPressure RegPressure;
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RegPressureTracker RPTracker;
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/// List of pressure sets that exceed the target's pressure limit before
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/// scheduling, listed in increasing set ID order. Each pressure set is paired
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/// with its max pressure in the currently scheduled regions.
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std::vector<PressureElement> RegionCriticalPSets;
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/// The top of the unscheduled zone.
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MachineBasicBlock::iterator CurrentTop;
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IntervalPressure TopPressure;
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RegPressureTracker TopRPTracker;
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/// The bottom of the unscheduled zone.
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MachineBasicBlock::iterator CurrentBottom;
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IntervalPressure BotPressure;
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RegPressureTracker BotRPTracker;
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#ifndef NDEBUG
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/// The number of instructions scheduled so far. Used to cut off the
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/// scheduler at the point determined by misched-cutoff.
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unsigned NumInstrsScheduled;
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#endif
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/// Total packets in the region.
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unsigned TotalPackets;
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const MachineLoopInfo *MLI;
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public:
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VLIWMachineScheduler(MachineSchedContext *C, MachineSchedStrategy *S):
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ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
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AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
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RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
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CurrentBottom(), BotRPTracker(BotPressure), MLI(C->MLI) {
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TopResourceModel = new VLIWResourceModel(C, InstrItins);
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BotResourceModel = new VLIWResourceModel(C, InstrItins);
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#ifndef NDEBUG
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NumInstrsScheduled = 0;
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#endif
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TotalPackets = 0;
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}
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virtual ~VLIWMachineScheduler() {
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delete SchedImpl;
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delete TopResourceModel;
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delete BotResourceModel;
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}
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MachineBasicBlock::iterator top() const { return CurrentTop; }
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MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
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/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
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/// region. This covers all instructions in a block, while schedule() may only
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/// cover a subset.
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void enterRegion(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endcount);
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void schedule();
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unsigned CurCycle;
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/// Get current register pressure for the top scheduled instructions.
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const IntervalPressure &getTopPressure() const { return TopPressure; }
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const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
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/// Get current register pressure for the bottom scheduled instructions.
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const IntervalPressure &getBotPressure() const { return BotPressure; }
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const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
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/// Get register pressure for the entire scheduling region before scheduling.
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const IntervalPressure &getRegPressure() const { return RegPressure; }
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const std::vector<PressureElement> &getRegionCriticalPSets() const {
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return RegionCriticalPSets;
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}
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VLIWResourceModel *getTopResourceModel() { return TopResourceModel; };
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VLIWResourceModel *getBotResourceModel() { return BotResourceModel; };
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/// getIssueWidth - Return the max instructions per scheduling group.
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unsigned getIssueWidth() const {
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return (InstrItins && InstrItins->SchedModel)
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? InstrItins->SchedModel->IssueWidth : 1;
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}
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/// getNumMicroOps - Return the number of issue slots required for this MI.
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unsigned getNumMicroOps(MachineInstr *MI) const {
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if (!InstrItins) return 1;
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int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
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return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
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}
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private:
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void scheduleNodeTopDown(SUnit *SU);
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void listScheduleTopDown();
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void initRegPressure();
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void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
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void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
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bool checkSchedLimit();
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void releaseRoots();
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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void releasePred(SUnit *SU, SDep *PredEdge);
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void releasePredecessors(SUnit *SU);
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void placeDebugValues();
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};
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} // namespace
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#endif
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