mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-29 11:29:39 +00:00
d258eb3ec5
into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
710 B
LLVM
36 lines
710 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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entry:
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; CHECK: f1:
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; CHECK: subs r0, r0, r2
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; CHECK: sbcs r1, r3
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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entry:
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; CHECK: f2:
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; CHECK: adds r0, r0, r0
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; CHECK: adcs r1, r1
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; CHECK: subs r0, r0, r2
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; CHECK: sbcs r1, r3
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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; rdar://12559385
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define i64 @f3(i32 %vi) {
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entry:
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; CHECK: f3:
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; CHECK: movw [[REG:r[0-9]+]], #36102
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; CHECK: sbcs r{{[0-9]+}}, [[REG]]
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%v0 = zext i32 %vi to i64
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%v1 = xor i64 %v0, -155057456198619
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%v4 = add i64 %v1, 155057456198619
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%v5 = add i64 %v4, %v1
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ret i64 %v5
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}
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