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https://github.com/c64scene-ar/llvm-6502.git
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27b1252c13
This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
3.9 KiB
LLVM
140 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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; This tests fcmp operations that do not map directly to NEON instructions.
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; une is implemented with VCEQ/VMVN
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define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcunef32:
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;CHECK: vceq.f32
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp une <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; olt is implemented with VCGT
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define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcoltf32:
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;CHECK: vcgt.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp olt <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; ole is implemented with VCGE
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define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcolef32:
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;CHECK: vcge.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp ole <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; uge is implemented with VCGT/VMVN
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define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcugef32:
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;CHECK: vcgt.f32
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp uge <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; ule is implemented with VCGT/VMVN
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define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vculef32:
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;CHECK: vcgt.f32
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp ule <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; ugt is implemented with VCGE/VMVN
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define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcugtf32:
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;CHECK: vcge.f32
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp ugt <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; ult is implemented with VCGE/VMVN
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define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcultf32:
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;CHECK: vcge.f32
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp ult <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; ueq is implemented with VCGT/VCGT/VORR/VMVN
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define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcueqf32:
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;CHECK: vcgt.f32
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;CHECK-NEXT: vcgt.f32
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;CHECK-NEXT: vorr
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp ueq <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; one is implemented with VCGT/VCGT/VORR
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define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vconef32:
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;CHECK: vcgt.f32
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;CHECK-NEXT: vcgt.f32
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;CHECK-NEXT: vorr
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp one <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; uno is implemented with VCGT/VCGE/VORR/VMVN
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define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcunof32:
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;CHECK: vcge.f32
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;CHECK-NEXT: vcgt.f32
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;CHECK-NEXT: vorr
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;CHECK-NEXT: vmvn
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp uno <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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; ord is implemented with VCGT/VCGE/VORR
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define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vcordf32:
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;CHECK: vcge.f32
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;CHECK-NEXT: vcgt.f32
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;CHECK-NEXT: vorr
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = fcmp ord <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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