mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
8f2a85e099
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
2.3 KiB
LLVM
94 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-ios7.0 -o - %s | FileCheck %s
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define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
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; CHECK-LABEL: test_return:
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
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; CHECK: cmp [[LOADED]], w1
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; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
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; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
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; CHECK: cbnz [[STATUS]], [[LOOP]]
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; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: orr w0, wzr, #0x1
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; CHECK: ret
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; CHECK: [[FAILED]]:
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; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: mov w0, wzr
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; CHECK: ret
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%pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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%conv = zext i1 %success to i32
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ret i32 %conv
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}
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define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
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; CHECK-LABEL: test_return_bool:
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxrb [[LOADED:w[0-9]+]], [x0]
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; CHECK: cmp [[LOADED]], w1, uxtb
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; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
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; CHECK: stlxrb [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
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; CHECK: cbnz [[STATUS]], [[LOOP]]
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; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; FIXME: DAG combine should be able to deal with this.
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; CHECK: orr [[TMP:w[0-9]+]], wzr, #0x1
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; CHECK: eor w0, [[TMP]], #0x1
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; CHECK: ret
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; CHECK: [[FAILED]]:
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; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: mov [[TMP:w[0-9]+]], wzr
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; CHECK: eor w0, [[TMP]], #0x1
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; CHECK: ret
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%pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic
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%success = extractvalue { i8, i1 } %pair, 1
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%failure = xor i1 %success, 1
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ret i1 %failure
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}
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define void @test_conditional(i32* %p, i32 %oldval, i32 %newval) {
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; CHECK-LABEL: test_conditional:
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
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; CHECK: cmp [[LOADED]], w1
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; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
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; CHECK: stlxr [[STATUS:w[0-9]+]], w2, [x0]
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; CHECK: cbnz [[STATUS]], [[LOOP]]
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; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: b _bar
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; CHECK: [[FAILED]]:
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; CHECK-NOT: cmp {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK: b _baz
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%pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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br i1 %success, label %true, label %false
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true:
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tail call void @bar() #2
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br label %end
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false:
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tail call void @baz() #2
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br label %end
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end:
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ret void
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}
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declare void @bar()
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declare void @baz()
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