mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
447 lines
16 KiB
LLVM
447 lines
16 KiB
LLVM
; Test the MSA intrinsics that are encoded with the 3R instruction format.
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; There are lots of these so this covers those beginning with 'c'
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_ceq_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_ceq_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_ceq_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_ceq_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.ceq.b(<16 x i8> %0, <16 x i8> %1)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_ceq_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.ceq.b(<16 x i8>, <16 x i8>) nounwind
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; CHECK: llvm_mips_ceq_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: ceq.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_ceq_b_test
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;
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@llvm_mips_ceq_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_ceq_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_ceq_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_ceq_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_ceq_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_ceq_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.ceq.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_ceq_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.ceq.h(<8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_ceq_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: ceq.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_ceq_h_test
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;
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@llvm_mips_ceq_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_ceq_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_ceq_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_ceq_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_ceq_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_ceq_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.ceq.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_ceq_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.ceq.w(<4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_ceq_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: ceq.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_ceq_w_test
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;
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@llvm_mips_ceq_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_ceq_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_ceq_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_ceq_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_ceq_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_ceq_d_ARG2
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%2 = tail call <2 x i64> @llvm.mips.ceq.d(<2 x i64> %0, <2 x i64> %1)
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store <2 x i64> %2, <2 x i64>* @llvm_mips_ceq_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.ceq.d(<2 x i64>, <2 x i64>) nounwind
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; CHECK: llvm_mips_ceq_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: ceq.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_ceq_d_test
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;
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@llvm_mips_cle_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_cle_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_cle_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_cle_s_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_cle_s_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_cle_s_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.cle.s.b(<16 x i8> %0, <16 x i8> %1)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_cle_s_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.cle.s.b(<16 x i8>, <16 x i8>) nounwind
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; CHECK: llvm_mips_cle_s_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: cle_s.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_cle_s_b_test
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;
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@llvm_mips_cle_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_cle_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_cle_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_cle_s_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_cle_s_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_cle_s_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.cle.s.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_cle_s_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.cle.s.h(<8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_cle_s_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: cle_s.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_cle_s_h_test
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;
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@llvm_mips_cle_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_cle_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_cle_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_cle_s_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_cle_s_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_cle_s_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.cle.s.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_cle_s_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.cle.s.w(<4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_cle_s_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: cle_s.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_cle_s_w_test
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;
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@llvm_mips_cle_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_cle_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_cle_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_cle_s_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_cle_s_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_cle_s_d_ARG2
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%2 = tail call <2 x i64> @llvm.mips.cle.s.d(<2 x i64> %0, <2 x i64> %1)
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store <2 x i64> %2, <2 x i64>* @llvm_mips_cle_s_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.cle.s.d(<2 x i64>, <2 x i64>) nounwind
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; CHECK: llvm_mips_cle_s_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: cle_s.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_cle_s_d_test
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;
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@llvm_mips_cle_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_cle_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_cle_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_cle_u_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_cle_u_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_cle_u_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.cle.u.b(<16 x i8> %0, <16 x i8> %1)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_cle_u_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.cle.u.b(<16 x i8>, <16 x i8>) nounwind
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; CHECK: llvm_mips_cle_u_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: cle_u.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_cle_u_b_test
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;
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@llvm_mips_cle_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_cle_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_cle_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_cle_u_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_cle_u_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_cle_u_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.cle.u.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_cle_u_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.cle.u.h(<8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_cle_u_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: cle_u.h
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; CHECK: st.h
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; CHECK: .size llvm_mips_cle_u_h_test
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;
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@llvm_mips_cle_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_cle_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_cle_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_cle_u_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_cle_u_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_cle_u_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.cle.u.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_cle_u_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.cle.u.w(<4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_cle_u_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: cle_u.w
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; CHECK: st.w
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; CHECK: .size llvm_mips_cle_u_w_test
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;
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@llvm_mips_cle_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_cle_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_cle_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_cle_u_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_cle_u_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_cle_u_d_ARG2
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%2 = tail call <2 x i64> @llvm.mips.cle.u.d(<2 x i64> %0, <2 x i64> %1)
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store <2 x i64> %2, <2 x i64>* @llvm_mips_cle_u_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.cle.u.d(<2 x i64>, <2 x i64>) nounwind
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; CHECK: llvm_mips_cle_u_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: cle_u.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_cle_u_d_test
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;
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@llvm_mips_clt_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_clt_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_clt_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_clt_s_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_clt_s_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_clt_s_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.clt.s.b(<16 x i8> %0, <16 x i8> %1)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_clt_s_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.clt.s.b(<16 x i8>, <16 x i8>) nounwind
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; CHECK: llvm_mips_clt_s_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: clt_s.b
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; CHECK: st.b
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; CHECK: .size llvm_mips_clt_s_b_test
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;
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@llvm_mips_clt_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_clt_s_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_clt_s_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
|
|
|
define void @llvm_mips_clt_s_h_test() nounwind {
|
|
entry:
|
|
%0 = load <8 x i16>* @llvm_mips_clt_s_h_ARG1
|
|
%1 = load <8 x i16>* @llvm_mips_clt_s_h_ARG2
|
|
%2 = tail call <8 x i16> @llvm.mips.clt.s.h(<8 x i16> %0, <8 x i16> %1)
|
|
store <8 x i16> %2, <8 x i16>* @llvm_mips_clt_s_h_RES
|
|
ret void
|
|
}
|
|
|
|
declare <8 x i16> @llvm.mips.clt.s.h(<8 x i16>, <8 x i16>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_s_h_test:
|
|
; CHECK: ld.h
|
|
; CHECK: ld.h
|
|
; CHECK: clt_s.h
|
|
; CHECK: st.h
|
|
; CHECK: .size llvm_mips_clt_s_h_test
|
|
;
|
|
@llvm_mips_clt_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_clt_s_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
|
@llvm_mips_clt_s_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
|
|
|
define void @llvm_mips_clt_s_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>* @llvm_mips_clt_s_w_ARG1
|
|
%1 = load <4 x i32>* @llvm_mips_clt_s_w_ARG2
|
|
%2 = tail call <4 x i32> @llvm.mips.clt.s.w(<4 x i32> %0, <4 x i32> %1)
|
|
store <4 x i32> %2, <4 x i32>* @llvm_mips_clt_s_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x i32> @llvm.mips.clt.s.w(<4 x i32>, <4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_s_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: clt_s.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_clt_s_w_test
|
|
;
|
|
@llvm_mips_clt_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
|
@llvm_mips_clt_s_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
|
@llvm_mips_clt_s_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
|
|
|
define void @llvm_mips_clt_s_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x i64>* @llvm_mips_clt_s_d_ARG1
|
|
%1 = load <2 x i64>* @llvm_mips_clt_s_d_ARG2
|
|
%2 = tail call <2 x i64> @llvm.mips.clt.s.d(<2 x i64> %0, <2 x i64> %1)
|
|
store <2 x i64> %2, <2 x i64>* @llvm_mips_clt_s_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x i64> @llvm.mips.clt.s.d(<2 x i64>, <2 x i64>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_s_d_test:
|
|
; CHECK: ld.d
|
|
; CHECK: ld.d
|
|
; CHECK: clt_s.d
|
|
; CHECK: st.d
|
|
; CHECK: .size llvm_mips_clt_s_d_test
|
|
;
|
|
@llvm_mips_clt_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
|
@llvm_mips_clt_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
|
@llvm_mips_clt_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
|
|
|
define void @llvm_mips_clt_u_b_test() nounwind {
|
|
entry:
|
|
%0 = load <16 x i8>* @llvm_mips_clt_u_b_ARG1
|
|
%1 = load <16 x i8>* @llvm_mips_clt_u_b_ARG2
|
|
%2 = tail call <16 x i8> @llvm.mips.clt.u.b(<16 x i8> %0, <16 x i8> %1)
|
|
store <16 x i8> %2, <16 x i8>* @llvm_mips_clt_u_b_RES
|
|
ret void
|
|
}
|
|
|
|
declare <16 x i8> @llvm.mips.clt.u.b(<16 x i8>, <16 x i8>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_u_b_test:
|
|
; CHECK: ld.b
|
|
; CHECK: ld.b
|
|
; CHECK: clt_u.b
|
|
; CHECK: st.b
|
|
; CHECK: .size llvm_mips_clt_u_b_test
|
|
;
|
|
@llvm_mips_clt_u_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
|
@llvm_mips_clt_u_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
|
@llvm_mips_clt_u_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
|
|
|
define void @llvm_mips_clt_u_h_test() nounwind {
|
|
entry:
|
|
%0 = load <8 x i16>* @llvm_mips_clt_u_h_ARG1
|
|
%1 = load <8 x i16>* @llvm_mips_clt_u_h_ARG2
|
|
%2 = tail call <8 x i16> @llvm.mips.clt.u.h(<8 x i16> %0, <8 x i16> %1)
|
|
store <8 x i16> %2, <8 x i16>* @llvm_mips_clt_u_h_RES
|
|
ret void
|
|
}
|
|
|
|
declare <8 x i16> @llvm.mips.clt.u.h(<8 x i16>, <8 x i16>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_u_h_test:
|
|
; CHECK: ld.h
|
|
; CHECK: ld.h
|
|
; CHECK: clt_u.h
|
|
; CHECK: st.h
|
|
; CHECK: .size llvm_mips_clt_u_h_test
|
|
;
|
|
@llvm_mips_clt_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_clt_u_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
|
@llvm_mips_clt_u_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
|
|
|
define void @llvm_mips_clt_u_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>* @llvm_mips_clt_u_w_ARG1
|
|
%1 = load <4 x i32>* @llvm_mips_clt_u_w_ARG2
|
|
%2 = tail call <4 x i32> @llvm.mips.clt.u.w(<4 x i32> %0, <4 x i32> %1)
|
|
store <4 x i32> %2, <4 x i32>* @llvm_mips_clt_u_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x i32> @llvm.mips.clt.u.w(<4 x i32>, <4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_u_w_test:
|
|
; CHECK: ld.w
|
|
; CHECK: ld.w
|
|
; CHECK: clt_u.w
|
|
; CHECK: st.w
|
|
; CHECK: .size llvm_mips_clt_u_w_test
|
|
;
|
|
@llvm_mips_clt_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
|
@llvm_mips_clt_u_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
|
@llvm_mips_clt_u_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
|
|
|
define void @llvm_mips_clt_u_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x i64>* @llvm_mips_clt_u_d_ARG1
|
|
%1 = load <2 x i64>* @llvm_mips_clt_u_d_ARG2
|
|
%2 = tail call <2 x i64> @llvm.mips.clt.u.d(<2 x i64> %0, <2 x i64> %1)
|
|
store <2 x i64> %2, <2 x i64>* @llvm_mips_clt_u_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x i64> @llvm.mips.clt.u.d(<2 x i64>, <2 x i64>) nounwind
|
|
|
|
; CHECK: llvm_mips_clt_u_d_test:
|
|
; CHECK: ld.d
|
|
; CHECK: ld.d
|
|
; CHECK: clt_u.d
|
|
; CHECK: st.d
|
|
; CHECK: .size llvm_mips_clt_u_d_test
|
|
;
|