mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
27b1252c13
This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
376 lines
14 KiB
LLVM
376 lines
14 KiB
LLVM
; RUN: llc -mtriple=arm -mattr=+neon %s -o - | FileCheck %s
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define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst1lanei8:
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;Check the (default) alignment.
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;CHECK: vst1.8 {d16[3]}, [r0]
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%tmp1 = load <8 x i8>* %B
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%tmp2 = extractelement <8 x i8> %tmp1, i32 3
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store i8 %tmp2, i8* %A, align 8
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst1lanei8_update:
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;CHECK: vst1.8 {d16[3]}, [{{r[0-9]}}]!
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%A = load i8** %ptr
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%tmp1 = load <8 x i8>* %B
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%tmp2 = extractelement <8 x i8> %tmp1, i32 3
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store i8 %tmp2, i8* %A, align 8
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%tmp3 = getelementptr i8* %A, i32 1
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store i8* %tmp3, i8** %ptr
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ret void
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}
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define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst1lanei16:
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vst1.16 {d16[2]}, [r0:16]
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%tmp1 = load <4 x i16>* %B
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%tmp2 = extractelement <4 x i16> %tmp1, i32 2
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store i16 %tmp2, i16* %A, align 8
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ret void
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}
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define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst1lanei32:
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;Check the alignment value. Max for this instruction is 32 bits:
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;CHECK: vst1.32 {d16[1]}, [r0:32]
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%tmp1 = load <2 x i32>* %B
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%tmp2 = extractelement <2 x i32> %tmp1, i32 1
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store i32 %tmp2, i32* %A, align 8
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ret void
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}
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define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst1lanef:
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;CHECK: vst1.32 {d16[1]}, [r0:32]
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%tmp1 = load <2 x float>* %B
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%tmp2 = extractelement <2 x float> %tmp1, i32 1
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store float %tmp2, float* %A
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ret void
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}
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define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vst1laneQi8:
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; // Can use scalar load. No need to use vectors.
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; // CHE-CK: vst1.8 {d17[1]}, [r0]
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%tmp1 = load <16 x i8>* %B
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%tmp2 = extractelement <16 x i8> %tmp1, i32 9
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store i8 %tmp2, i8* %A, align 8
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ret void
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}
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define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst1laneQi16:
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;CHECK: vst1.16 {d17[1]}, [r0:16]
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%tmp1 = load <8 x i16>* %B
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%tmp2 = extractelement <8 x i16> %tmp1, i32 5
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store i16 %tmp2, i16* %A, align 8
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ret void
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}
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define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst1laneQi32:
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; // Can use scalar load. No need to use vectors.
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; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
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%tmp1 = load <4 x i32>* %B
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%tmp2 = extractelement <4 x i32> %tmp1, i32 3
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store i32 %tmp2, i32* %A, align 8
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst1laneQi32_update:
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; // Can use scalar load. No need to use vectors.
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; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
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%A = load i32** %ptr
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%tmp1 = load <4 x i32>* %B
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%tmp2 = extractelement <4 x i32> %tmp1, i32 3
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store i32 %tmp2, i32* %A, align 8
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%tmp3 = getelementptr i32* %A, i32 1
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store i32* %tmp3, i32** %ptr
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ret void
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}
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define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst1laneQf:
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; // Can use scalar load. No need to use vectors.
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; // CHE-CK: vst1.32 {d17[1]}, [r0]
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%tmp1 = load <4 x float>* %B
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%tmp2 = extractelement <4 x float> %tmp1, i32 3
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store float %tmp2, float* %A
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ret void
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}
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define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst2lanei8:
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;Check the alignment value. Max for this instruction is 16 bits:
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;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 4)
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ret void
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}
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define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst2lanei16:
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;Check the alignment value. Max for this instruction is 32 bits:
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;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
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ret void
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}
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;Check for a post-increment updating store with register increment.
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define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
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;CHECK-LABEL: vst2lanei16_update:
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;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
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%A = load i16** %ptr
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 2)
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%tmp2 = getelementptr i16* %A, i32 %inc
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store i16* %tmp2, i16** %ptr
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ret void
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}
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define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst2lanei32:
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;CHECK: vst2.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst2lanef:
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;CHECK: vst2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst2laneQi16:
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;Check the (default) alignment.
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;CHECK: vst2.16 {d17[1], d19[1]}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1)
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ret void
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}
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define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst2laneQi32:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16)
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ret void
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}
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define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst2laneQf:
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;CHECK: vst2.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst2lane.v8i8(i8*, <8 x i8>, <8 x i8>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v4i16(i8*, <4 x i16>, <4 x i16>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v2i32(i8*, <2 x i32>, <2 x i32>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v2f32(i8*, <2 x float>, <2 x float>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
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define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst3lanei8:
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;CHECK: vst3.8
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst3lanei16:
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;Check the (default) alignment value. VST3 does not support alignment.
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;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8)
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ret void
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}
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define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst3lanei32:
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;CHECK: vst3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst3lanef:
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;CHECK: vst3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst3laneQi16:
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;Check the (default) alignment value. VST3 does not support alignment.
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;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6, i32 8)
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ret void
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}
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define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst3laneQi32:
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;CHECK: vst3.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst3laneQi32_update:
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;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
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%A = load i32** %ptr
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0, i32 1)
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%tmp2 = getelementptr i32* %A, i32 3
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store i32* %tmp2, i32** %ptr
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ret void
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}
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define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst3laneQf:
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;CHECK: vst3.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
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declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
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define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst4lanei8:
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;Check the alignment value. Max for this instruction is 32 bits:
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;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst4lanei8_update:
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;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
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%A = load i8** %ptr
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8)
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%tmp2 = getelementptr i8* %A, i32 4
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store i8* %tmp2, i8** %ptr
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ret void
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}
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define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst4lanei16:
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;CHECK: vst4.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst4lanei32:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 16)
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ret void
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}
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define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst4lanef:
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;CHECK: vst4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1, i32 1)
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ret void
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}
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define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst4laneQi16:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7, i32 16)
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ret void
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|
}
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|
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define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst4laneQi32:
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|
;Check the (default) alignment.
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|
;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
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%tmp0 = bitcast i32* %A to i8*
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|
%tmp1 = load <4 x i32>* %B
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|
call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1)
|
|
ret void
|
|
}
|
|
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|
define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
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|
;CHECK-LABEL: vst4laneQf:
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|
;CHECK: vst4.32
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|
%tmp0 = bitcast float* %A to i8*
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|
%tmp1 = load <4 x float>* %B
|
|
call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
|
|
ret void
|
|
}
|
|
|
|
; Make sure this doesn't crash; PR10258
|
|
define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
|
|
;CHECK-LABEL: variable_insertelement:
|
|
%r = insertelement <8 x i16> %a, i16 %b, i32 %c
|
|
ret <8 x i16> %r
|
|
}
|
|
|
|
declare void @llvm.arm.neon.vst4lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32, i32) nounwind
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|
declare void @llvm.arm.neon.vst4lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind
|
|
declare void @llvm.arm.neon.vst4lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind
|
|
declare void @llvm.arm.neon.vst4lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32, i32) nounwind
|
|
|
|
declare void @llvm.arm.neon.vst4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind
|
|
declare void @llvm.arm.neon.vst4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind
|
|
declare void @llvm.arm.neon.vst4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind
|