llvm-6502/test/CodeGen/X86/widen_conv-2.ll
Benjamin Kramer 3d5694dca9 Fix tests not to depend on specific regalloc or instruction order.
They were failing with -mcpu=atom.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192890 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-17 12:41:05 +00:00

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LLVM

; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: {{cwtl|movswl}}
; CHECK: {{cwtl|movswl}}
; sign extension v2i32 to v2i16
define void @convert(<2 x i32>* %dst.addr, <2 x i16> %src) nounwind {
entry:
%signext = sext <2 x i16> %src to <2 x i32> ; <<12 x i8>> [#uses=1]
store <2 x i32> %signext, <2 x i32>* %dst.addr
ret void
}