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a70dca156f
is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
252 lines
11 KiB
C++
252 lines
11 KiB
C++
//===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a simple register copy coalescing phase.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
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#define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/ADT/BitVector.h"
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namespace llvm {
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class SimpleRegisterCoalescing;
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class LiveVariables;
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class TargetRegisterInfo;
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class TargetInstrInfo;
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class VirtRegMap;
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class MachineLoopInfo;
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/// CopyRec - Representation for copy instructions in coalescer queue.
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///
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struct CopyRec {
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MachineInstr *MI;
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unsigned LoopDepth;
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CopyRec(MachineInstr *mi, unsigned depth)
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: MI(mi), LoopDepth(depth) {};
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};
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class SimpleRegisterCoalescing : public MachineFunctionPass,
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public RegisterCoalescer {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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LiveIntervals *li_;
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const MachineLoopInfo* loopInfo;
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AliasAnalysis *AA;
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BitVector allocatableRegs_;
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DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
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/// JoinedCopies - Keep track of copies eliminated due to coalescing.
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///
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SmallPtrSet<MachineInstr*, 32> JoinedCopies;
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/// ReMatCopies - Keep track of copies eliminated due to remat.
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///
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SmallPtrSet<MachineInstr*, 32> ReMatCopies;
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/// ReMatDefs - Keep track of definition instructions which have
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/// been remat'ed.
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SmallPtrSet<MachineInstr*, 8> ReMatDefs;
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public:
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static char ID; // Pass identifcation, replacement for typeid
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SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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};
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
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// This runs as an independent pass, so don't do anything.
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return false;
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};
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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private:
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/// joinIntervals - join compatible live intervals
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void joinIntervals();
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/// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
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/// copies that cannot yet be coalesced into the "TryAgain" list.
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void CopyCoalesceInMBB(MachineBasicBlock *MBB,
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std::vector<CopyRec> &TryAgain);
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/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
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/// which are the src/dst of the copy instruction CopyMI. This returns true
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/// if the copy was successfully coalesced away. If it is not currently
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/// possible to coalesce this interval, but it may be possible if other
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/// things get coalesced, then it returns true by reference in 'Again'.
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bool JoinCopy(CopyRec &TheCopy, bool &Again);
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/// JoinIntervals - Attempt to join these two intervals. On failure, this
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/// returns false. Otherwise, if one of the intervals being joined is a
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/// physreg, this method always canonicalizes DestInt to be it. The output
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/// "SrcInt" will not have been modified, so we can use this information
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/// below to update aliases.
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bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
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/// SimpleJoin - Attempt to join the specified interval into this one. The
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/// caller of this method must guarantee that the RHS only contains a single
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/// value number and that the RHS is not defined by a copy from this
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/// interval. This returns false if the intervals are not joinable, or it
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/// joins them and returns true.
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bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
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/// Return true if the two specified registers belong to different register
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/// classes. The registers may be either phys or virt regs.
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bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
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/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
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/// the source value number is defined by a copy from the destination reg
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/// see if we can merge these two destination reg valno# into a single
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/// value number, eliminating a copy.
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bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
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MachineInstr *CopyMI);
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/// HasOtherReachingDefs - Return true if there are definitions of IntB
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/// other than BValNo val# that can reach uses of AValno val# of IntA.
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bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
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VNInfo *AValNo, VNInfo *BValNo);
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/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
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/// If the source value number is defined by a commutable instruction and
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/// its other operand is coalesced to the copy dest register, see if we
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/// can transform the copy into a noop by commuting the definition.
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bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
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MachineInstr *CopyMI);
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/// TrimLiveIntervalToLastUse - If there is a last use in the same basic
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/// block as the copy instruction, trim the ive interval to the last use
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/// and return true.
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bool TrimLiveIntervalToLastUse(LiveIndex CopyIdx,
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MachineBasicBlock *CopyMBB,
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LiveInterval &li, const LiveRange *LR);
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/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
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/// computation, replace the copy by rematerialize the definition.
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bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
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unsigned DstSubIdx, MachineInstr *CopyMI);
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/// CanCoalesceWithImpDef - Returns true if the specified copy instruction
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/// from an implicit def to another register can be coalesced away.
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bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
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LiveInterval &li, LiveInterval &ImpLi) const;
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/// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
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/// implicit_def and it is being removed. Turn all copies from this value#
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/// into implicit_defs.
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void TurnCopiesFromValNoToImpDefs(LiveInterval &li, VNInfo *VNI);
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/// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
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/// a virtual destination register with physical source register.
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bool isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
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MachineBasicBlock *CopyMBB,
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LiveInterval &DstInt, LiveInterval &SrcInt);
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/// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
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/// copy from a virtual source register to a physical destination register.
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bool isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
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MachineBasicBlock *CopyMBB,
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LiveInterval &DstInt, LiveInterval &SrcInt);
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/// isWinToJoinCrossClass - Return true if it's profitable to coalesce
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/// two virtual registers from different register classes.
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bool isWinToJoinCrossClass(unsigned LargeReg, unsigned SmallReg,
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unsigned Threshold);
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/// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
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/// register with a physical register, check if any of the virtual register
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/// operand is a sub-register use or def. If so, make sure it won't result
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/// in an illegal extract_subreg or insert_subreg instruction.
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bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
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unsigned VirtReg, unsigned PhysReg);
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/// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
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/// an extract_subreg where dst is a physical register, e.g.
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/// cl = EXTRACT_SUBREG reg1024, 1
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bool CanJoinExtractSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
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unsigned SubIdx, unsigned &RealDstReg);
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/// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
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/// an insert_subreg where src is a physical register, e.g.
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/// reg1024 = INSERT_SUBREG reg1024, c1, 0
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bool CanJoinInsertSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
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unsigned SubIdx, unsigned &RealDstReg);
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/// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
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/// the specified live interval is defined by a copy from the specified
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/// register.
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bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
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unsigned Reg);
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/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
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/// update the subregister number if it is not zero. If DstReg is a
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/// physical register and the existing subregister number of the def / use
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/// being updated is not zero, make sure to set it to the correct physical
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/// subregister.
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void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
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/// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
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/// due to live range lengthening as the result of coalescing.
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void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
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/// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
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/// Return true if live interval is removed.
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bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
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/// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
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/// extended by a dead copy. Mark the last use (if any) of the val# as kill
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/// as ends the live range there. If there isn't another use, then this
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/// live range is dead. Return true if live interval is removed.
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bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
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/// RemoveDeadDef - If a def of a live interval is now determined dead,
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/// remove the val# it defines. If the live interval becomes empty, remove
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/// it as well.
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bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
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/// lastRegisterUse - Returns the last use of the specific register between
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/// cycles Start and End or NULL if there are no uses.
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MachineOperand *lastRegisterUse(LiveIndex Start,
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LiveIndex End, unsigned Reg,
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LiveIndex &LastUseIdx) const;
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/// CalculateSpillWeights - Compute spill weights for all virtual register
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/// live intervals.
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void CalculateSpillWeights();
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void printRegName(unsigned reg) const;
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};
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} // End llvm namespace
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#endif
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