mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
453 lines
18 KiB
TableGen
453 lines
18 KiB
TableGen
//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent interfaces which should be
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// implemented by each target which is using a TableGen based code generator.
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//
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//===----------------------------------------------------------------------===//
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// Include all information about LLVM intrinsics.
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include "llvm/Intrinsics.td"
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//===----------------------------------------------------------------------===//
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// Register file description - These classes are used to fill in the target
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// description classes.
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class RegisterClass; // Forward def
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// Register - You should define one instance of this class for each register
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// in the target machine. String n will become the "name" of the register.
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class Register<string n> {
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string Namespace = "";
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string Name = n;
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// SpillSize - If this value is set to a non-zero value, it is the size in
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// bits of the spill slot required to hold this register. If this value is
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// set to zero, the information is inferred from any register classes the
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// register belongs to.
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int SpillSize = 0;
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// SpillAlignment - This value is used to specify the alignment required for
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// spilling the register. Like SpillSize, this should only be explicitly
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// specified if the register is not in a register class.
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int SpillAlignment = 0;
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// Aliases - A list of registers that this register overlaps with. A read or
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// modification of this register can potentially read or modify the aliased
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// registers.
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list<Register> Aliases = [];
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// SubRegs - A list of registers that are parts of this register. Note these
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// are "immediate" sub-registers and the registers within the list do not
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// themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
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// not [AX, AH, AL].
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list<Register> SubRegs = [];
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// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
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// These values can be determined by locating the <target>.h file in the
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// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
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// order of these names correspond to the enumeration used by gcc. A value of
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// -1 indicates that the gcc number is undefined and -2 that register number
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// is invalid for this mode/flavour.
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list<int> DwarfNumbers = [];
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}
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// RegisterWithSubRegs - This can be used to define instances of Register which
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// need to specify sub-registers.
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// List "subregs" specifies which registers are sub-registers to this one. This
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// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
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// This allows the code generator to be careful not to put two values with
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// overlapping live ranges into registers which alias.
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class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
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let SubRegs = subregs;
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}
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// SubRegSet - This can be used to define a specific mapping of registers to
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// indices, for use as named subregs of a particular physical register. Each
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// register in 'subregs' becomes an addressable subregister at index 'n' of the
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// corresponding register in 'regs'.
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class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
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int index = n;
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list<Register> From = regs;
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list<Register> To = subregs;
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}
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// RegisterClass - Now that all of the registers are defined, and aliases
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// between registers are defined, specify which registers belong to which
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// register classes. This also defines the default allocation order of
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// registers by register allocators.
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//
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class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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list<Register> regList> {
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string Namespace = namespace;
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// RegType - Specify the list ValueType of the registers in this register
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// class. Note that all registers in a register class must have the same
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// ValueTypes. This is a list because some targets permit storing different
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// types in same register, for example vector values with 128-bit total size,
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// but different count/size of items, like SSE on x86.
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//
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list<ValueType> RegTypes = regTypes;
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// Size - Specify the spill size in bits of the registers. A default value of
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// zero lets tablgen pick an appropriate size.
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int Size = 0;
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// Alignment - Specify the alignment required of the registers when they are
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// stored or loaded to memory.
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//
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int Alignment = alignment;
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// CopyCost - This value is used to specify the cost of copying a value
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// between two registers in this register class. The default value is one
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// meaning it takes a single instruction to perform the copying. A negative
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// value means copying is extremely expensive or impossible.
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int CopyCost = 1;
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// MemberList - Specify which registers are in this class. If the
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// allocation_order_* method are not specified, this also defines the order of
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// allocation used by the register allocator.
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//
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list<Register> MemberList = regList;
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// SubClassList - Specify which register classes correspond to subregisters
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// of this class. The order should be by subregister set index.
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list<RegisterClass> SubRegClassList = [];
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// MethodProtos/MethodBodies - These members can be used to insert arbitrary
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// code into a generated register class. The normal usage of this is to
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// overload virtual methods.
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code MethodProtos = [{}];
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code MethodBodies = [{}];
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}
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//===----------------------------------------------------------------------===//
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// DwarfRegNum - This class provides a mapping of the llvm register enumeration
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// to the register numbering used by gcc and gdb. These values are used by a
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// debug information writer (ex. DwarfWriter) to describe where values may be
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// located during execution.
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class DwarfRegNum<list<int> Numbers> {
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// DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
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// These values can be determined by locating the <target>.h file in the
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// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
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// order of these names correspond to the enumeration used by gcc. A value of
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// -1 indicates that the gcc number is undefined and -2 that register number is
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// invalid for this mode/flavour.
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list<int> DwarfNumbers = Numbers;
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}
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//===----------------------------------------------------------------------===//
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// Pull in the common support for scheduling
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//
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include "TargetSchedule.td"
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class Predicate; // Forward def
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//===----------------------------------------------------------------------===//
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// Instruction set description - These classes correspond to the C++ classes in
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// the Target/TargetInstrInfo.h file.
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//
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class Instruction {
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string Namespace = "";
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dag OutOperandList; // An dag containing the MI def operand list.
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dag InOperandList; // An dag containing the MI use operand list.
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string AsmString = ""; // The .s format to print the instruction with.
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// Pattern - Set to the DAG pattern for this instruction, if we know of one,
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// otherwise, uninitialized.
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list<dag> Pattern;
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// The follow state will eventually be inferred automatically from the
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// instruction pattern.
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list<Register> Uses = []; // Default to using no non-operand registers
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list<Register> Defs = []; // Default to modifying no non-operand registers
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// Predicates - List of predicates which will be turned into isel matching
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// code.
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list<Predicate> Predicates = [];
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// Code size.
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int CodeSize = 0;
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// Added complexity passed onto matching pattern.
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int AddedComplexity = 0;
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// These bits capture information about the high-level semantics of the
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// instruction.
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isIndirectBranch = 0; // Is this instruction an indirect branch?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit isSimpleLoad = 0; // Is this just a load instruction?
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bit mayLoad = 0; // Is it possible for this inst to read memory?
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bit mayStore = 0; // Is it possible for this inst to write memory?
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bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
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bit isTwoAddress = 0; // Is this a two address instruction?
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bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
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bit isCommutable = 0; // Is this 3 operand instruction commutable?
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bit isTerminator = 0; // Is this part of the terminator for a basic block?
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bit isReMaterializable = 0; // Is this instruction re-materializable?
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bit isPredicable = 0; // Is this instruction predicable?
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bit hasDelaySlot = 0; // Does this instruction have an delay slot?
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bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
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bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
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// Side effect flags - When set, the flags have these meanings:
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//
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// hasSideEffects - The instruction has side effects that are not
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// captured by any operands of the instruction or other flags.
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// mayHaveSideEffects - Some instances of the instruction can have side
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// effects. The virtual method "isReallySideEffectFree" is called to
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// determine this. Load instructions are an example of where this is
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// useful. In general, loads always have side effects. However, loads from
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// constant pools don't. Individual back ends make this determination.
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// neverHasSideEffects - Set on an instruction with no pattern if it has no
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// side effects.
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bit hasSideEffects = 0;
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bit mayHaveSideEffects = 0;
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bit neverHasSideEffects = 0;
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InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
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string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
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/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
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/// be encoded into the output machineinstr.
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string DisableEncoding = "";
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}
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/// Predicates - These are extra conditionals which are turned into instruction
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/// selector matching code. Currently each predicate is just a string.
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class Predicate<string cond> {
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string CondString = cond;
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}
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/// NoHonorSignDependentRounding - This predicate is true if support for
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/// sign-dependent-rounding is not enabled.
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def NoHonorSignDependentRounding
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: Predicate<"!HonorSignDependentRoundingFPMath()">;
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class Requires<list<Predicate> preds> {
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list<Predicate> Predicates = preds;
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}
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/// ops definition - This is just a simple marker used to identify the operands
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/// list for an instruction. outs and ins are identical both syntatically and
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/// semantically, they are used to define def operands and use operands to
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/// improve readibility. This should be used like this:
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/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
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def ops;
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def outs;
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def ins;
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/// variable_ops definition - Mark this instruction as taking a variable number
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/// of operands.
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def variable_ops;
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/// ptr_rc definition - Mark this operand as being a pointer value whose
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/// register class is resolved dynamically via a callback to TargetInstrInfo.
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/// FIXME: We should probably change this to a class which contain a list of
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/// flags. But currently we have but one flag.
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def ptr_rc;
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/// Operand Types - These provide the built-in operand types that may be used
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/// by a target. Targets can optionally provide their own operand types as
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/// needed, though this should not be needed for RISC targets.
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class Operand<ValueType ty> {
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ValueType Type = ty;
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string PrintMethod = "printOperand";
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dag MIOperandInfo = (ops);
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}
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def i1imm : Operand<i1>;
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def i8imm : Operand<i8>;
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def i16imm : Operand<i16>;
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def i32imm : Operand<i32>;
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def i64imm : Operand<i64>;
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/// zero_reg definition - Special node to stand for the zero register.
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///
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def zero_reg;
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/// PredicateOperand - This can be used to define a predicate operand for an
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/// instruction. OpTypes specifies the MIOperandInfo for the operand, and
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/// AlwaysVal specifies the value of this predicate when set to "always
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/// execute".
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class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
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: Operand<ty> {
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let MIOperandInfo = OpTypes;
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dag DefaultOps = AlwaysVal;
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}
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/// OptionalDefOperand - This is used to define a optional definition operand
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/// for an instruction. DefaultOps is the register the operand represents if none
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/// is supplied, e.g. zero_reg.
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class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
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: Operand<ty> {
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let MIOperandInfo = OpTypes;
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dag DefaultOps = defaultops;
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}
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// InstrInfo - This class should only be instantiated once to provide parameters
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// which are global to the the target machine.
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//
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class InstrInfo {
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// If the target wants to associate some target-specific information with each
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// instruction, it should provide these two lists to indicate how to assemble
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// the target specific information into the 32 bits available.
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//
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list<string> TSFlagsFields = [];
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list<int> TSFlagsShifts = [];
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// Target can specify its instructions in either big or little-endian formats.
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// For instance, while both Sparc and PowerPC are big-endian platforms, the
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// Sparc manual specifies its instructions in the format [31..0] (big), while
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// PowerPC specifies them using the format [0..31] (little).
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bit isLittleEndianEncoding = 0;
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}
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// Standard Instructions.
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def PHI : Instruction {
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let OutOperandList = (ops);
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let InOperandList = (ops variable_ops);
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let AsmString = "PHINODE";
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let Namespace = "TargetInstrInfo";
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}
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def INLINEASM : Instruction {
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let OutOperandList = (ops);
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let InOperandList = (ops variable_ops);
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let AsmString = "";
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let Namespace = "TargetInstrInfo";
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}
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def LABEL : Instruction {
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let OutOperandList = (ops);
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let InOperandList = (ops i32imm:$id);
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let AsmString = "";
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let Namespace = "TargetInstrInfo";
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let hasCtrlDep = 1;
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}
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def EXTRACT_SUBREG : Instruction {
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let OutOperandList = (ops variable_ops);
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let InOperandList = (ops variable_ops);
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let AsmString = "";
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let Namespace = "TargetInstrInfo";
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let neverHasSideEffects = 1;
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}
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def INSERT_SUBREG : Instruction {
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let OutOperandList = (ops variable_ops);
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let InOperandList = (ops variable_ops);
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let AsmString = "";
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let Namespace = "TargetInstrInfo";
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let neverHasSideEffects = 1;
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}
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//===----------------------------------------------------------------------===//
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// AsmWriter - This class can be implemented by targets that need to customize
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// the format of the .s file writer.
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//
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// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
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// on X86 for example).
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//
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class AsmWriter {
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// AsmWriterClassName - This specifies the suffix to use for the asmwriter
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// class. Generated AsmWriter classes are always prefixed with the target
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// name.
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string AsmWriterClassName = "AsmPrinter";
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// InstFormatName - AsmWriters can specify the name of the format string to
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// print instructions with.
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string InstFormatName = "AsmString";
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// Variant - AsmWriters can be of multiple different variants. Variants are
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// used to support targets that need to emit assembly code in ways that are
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// mostly the same for different targets, but have minor differences in
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// syntax. If the asmstring contains {|} characters in them, this integer
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// will specify which alternative to use. For example "{x|y|z}" with Variant
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// == 1, will expand to "y".
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int Variant = 0;
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}
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def DefaultAsmWriter : AsmWriter;
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//===----------------------------------------------------------------------===//
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// Target - This class contains the "global" target information
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//
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class Target {
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// InstructionSet - Instruction set description for this target.
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InstrInfo InstructionSet;
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// AssemblyWriters - The AsmWriter instances available for this target.
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list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
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}
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//===----------------------------------------------------------------------===//
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// SubtargetFeature - A characteristic of the chip set.
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//
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class SubtargetFeature<string n, string a, string v, string d,
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list<SubtargetFeature> i = []> {
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// Name - Feature name. Used by command line (-mattr=) to determine the
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// appropriate target chip.
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//
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string Name = n;
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// Attribute - Attribute to be set by feature.
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//
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string Attribute = a;
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// Value - Value the attribute to be set to by feature.
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//
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string Value = v;
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// Desc - Feature description. Used by command line (-mattr=) to display help
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// information.
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//
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string Desc = d;
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// Implies - Features that this feature implies are present. If one of those
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// features isn't set, then this one shouldn't be set either.
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//
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list<SubtargetFeature> Implies = i;
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}
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//===----------------------------------------------------------------------===//
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// Processor chip sets - These values represent each of the chip sets supported
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// by the scheduler. Each Processor definition requires corresponding
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// instruction itineraries.
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//
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class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
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// Name - Chip set name. Used by command line (-mcpu=) to determine the
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// appropriate target chip.
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//
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string Name = n;
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// ProcItin - The scheduling information for the target processor.
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//
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ProcessorItineraries ProcItin = pi;
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// Features - list of
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list<SubtargetFeature> Features = f;
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}
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//===----------------------------------------------------------------------===//
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// Pull in the common support for calling conventions.
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//
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include "TargetCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Pull in the common support for DAG isel generation.
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//
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include "TargetSelectionDAG.td"
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