mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4354 91177308-0d34-0410-b5e6-96231b3b80d8
1764 lines
63 KiB
C++
1764 lines
63 KiB
C++
//===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
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//
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// This file contains implementation of Sparc specific helper methods
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// used for register allocation.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInternals.h"
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#include "SparcRegClassInfo.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrAnnot.h"
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#include "llvm/CodeGen/RegAllocCommon.h"
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#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
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#include "llvm/iTerminators.h"
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#include "llvm/iOther.h"
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#include "llvm/Function.h"
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#include "llvm/DerivedTypes.h"
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#include <iostream>
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#include <values.h>
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using std::cerr;
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using std::vector;
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UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
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: MachineRegInfo(tgt), NumOfIntArgRegs(6),
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NumOfFloatArgRegs(32), InvalidRegNum(1000) {
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MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
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MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
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MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
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MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
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assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
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"32 Float regs are used for float arg passing");
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}
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// getZeroRegNum - returns the register that contains always zero.
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// this is the unified register number
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//
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int UltraSparcRegInfo::getZeroRegNum() const {
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::g0);
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}
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// getCallAddressReg - returns the reg used for pushing the address when a
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// method is called. This can be used for other purposes between calls
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//
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unsigned UltraSparcRegInfo::getCallAddressReg() const {
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::o7);
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}
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// Returns the register containing the return address.
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// It should be made sure that this register contains the return
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// value when a return instruction is reached.
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//
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unsigned UltraSparcRegInfo::getReturnAddressReg() const {
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::i7);
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}
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// Register get name implementations...
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// Int register names in same order as enum in class SparcIntRegClass
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static const char * const IntRegNames[] = {
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"o0", "o1", "o2", "o3", "o4", "o5", "o7",
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"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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"i0", "i1", "i2", "i3", "i4", "i5",
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"i6", "i7",
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"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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"o6"
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};
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const char * const SparcIntRegClass::getRegName(unsigned reg) {
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assert(reg < NumOfAllRegs);
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return IntRegNames[reg];
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}
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static const char * const FloatRegNames[] = {
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
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"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
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"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
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"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
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"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
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"f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
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"f60", "f61", "f62", "f63"
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};
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const char * const SparcFloatRegClass::getRegName(unsigned reg) {
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assert (reg < NumOfAllRegs);
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return FloatRegNames[reg];
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}
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static const char * const IntCCRegNames[] = {
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"xcc", "ccr"
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};
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const char * const SparcIntCCRegClass::getRegName(unsigned reg) {
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assert(reg < 2);
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return IntCCRegNames[reg];
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}
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static const char * const FloatCCRegNames[] = {
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"fcc0", "fcc1", "fcc2", "fcc3"
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};
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const char * const SparcFloatCCRegClass::getRegName(unsigned reg) {
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assert (reg < 4);
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return FloatCCRegNames[reg];
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}
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// given the unified register number, this gives the name
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// for generating assembly code or debugging.
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//
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const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const {
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if( reg < 32 )
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return SparcIntRegClass::getRegName(reg);
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else if ( reg < (64 + 32) )
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return SparcFloatRegClass::getRegName( reg - 32);
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else if( reg < (64+32+4) )
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return SparcFloatCCRegClass::getRegName( reg -32 - 64);
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else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
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return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4);
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else if (reg== InvalidRegNum) //****** TODO: Remove */
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return "<*NoReg*>";
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else
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assert(0 && "Invalid register number");
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return "";
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}
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// Get unified reg number for frame pointer
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unsigned UltraSparcRegInfo::getFramePointer() const {
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::i6);
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}
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// Get unified reg number for stack pointer
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unsigned UltraSparcRegInfo::getStackPointer() const {
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return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
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SparcIntRegClass::o6);
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}
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//---------------------------------------------------------------------------
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// Finds whether a call is an indirect call
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//---------------------------------------------------------------------------
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inline bool
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isVarArgsFunction(const Type *funcType) {
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return cast<FunctionType>(cast<PointerType>(funcType)
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->getElementType())->isVarArg();
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}
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inline bool
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isVarArgsCall(const MachineInstr *CallMI) {
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Value* callee = CallMI->getOperand(0).getVRegValue();
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// const Type* funcType = isa<Function>(callee)? callee->getType()
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// : cast<PointerType>(callee->getType())->getElementType();
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const Type* funcType = callee->getType();
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return isVarArgsFunction(funcType);
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}
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// Get the register number for the specified integer arg#,
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// assuming there are argNum total args, intArgNum int args,
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// and fpArgNum FP args preceding (and not including) this one.
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// Use INT regs for FP args if this is a varargs call.
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//
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// Return value:
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// InvalidRegNum, if there is no int register available for the arg.
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// regNum, otherwise (this is NOT the unified reg. num).
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//
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inline int
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UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
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unsigned argNo,
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unsigned intArgNo, unsigned fpArgNo,
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unsigned& regClassId) const
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{
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regClassId = IntRegClassID;
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if (argNo >= NumOfIntArgRegs)
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return InvalidRegNum;
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else
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return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
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}
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// Get the register number for the specified FP arg#,
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// assuming there are argNum total args, intArgNum int args,
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// and fpArgNum FP args preceding (and not including) this one.
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// Use INT regs for FP args if this is a varargs call.
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//
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// Return value:
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// InvalidRegNum, if there is no int register available for the arg.
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// regNum, otherwise (this is NOT the unified reg. num).
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//
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inline int
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UltraSparcRegInfo::regNumForFPArg(unsigned regType,
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bool inCallee, bool isVarArgsCall,
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unsigned argNo,
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unsigned intArgNo, unsigned fpArgNo,
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unsigned& regClassId) const
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{
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if (isVarArgsCall)
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return regNumForIntArg(inCallee, isVarArgsCall, argNo, intArgNo, fpArgNo,
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regClassId);
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else
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{
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regClassId = FloatRegClassID;
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if (regType == FPSingleRegType)
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return (argNo*2+1 >= NumOfFloatArgRegs)?
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InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2 + 1);
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else if (regType == FPDoubleRegType)
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return (argNo*2 >= NumOfFloatArgRegs)?
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InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2);
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else
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assert(0 && "Illegal FP register type");
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return 0;
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}
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}
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//---------------------------------------------------------------------------
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// Finds the return address of a call sparc specific call instruction
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//---------------------------------------------------------------------------
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// The following 4 methods are used to find the RegType (SparcInternals.h)
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// of a LiveRange, a Value, and for a given register unified reg number.
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//
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int UltraSparcRegInfo::getRegType(unsigned regClassID,
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const Type* type) const {
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switch (regClassID) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID: {
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if (type == Type::FloatTy)
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return FPSingleRegType;
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else if (type == Type::DoubleTy)
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return FPDoubleRegType;
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assert(0 && "Unknown type in FloatRegClass");
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}
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType;
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default: assert( 0 && "Unknown reg class ID"); return 0;
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}
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}
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int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
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return getRegType(LR->getRegClass()->getID(), LR->getType());
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}
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int UltraSparcRegInfo::getRegType(const Value *Val) const {
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return getRegType(getRegClassIDOfValue(Val), Val->getType());
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}
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int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
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if (unifiedRegNum < 32)
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return IntRegType;
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else if (unifiedRegNum < (32 + 32))
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return FPSingleRegType;
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else if (unifiedRegNum < (64 + 32))
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return FPDoubleRegType;
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else if (unifiedRegNum < (64+32+4))
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return FloatCCRegType;
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else if (unifiedRegNum < (64+32+4+2))
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return IntCCRegType;
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else
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assert(0 && "Invalid unified register number in getRegType");
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return 0;
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}
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// To find the register class used for a specified Type
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//
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unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
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bool isCCReg) const {
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Type::PrimitiveID ty = type->getPrimitiveID();
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unsigned res;
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// FIXME: Comparing types like this isn't very safe...
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if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
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(ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
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res = IntRegClassID; // sparc int reg (ty=0: void)
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else if (ty <= Type::DoubleTyID)
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res = FloatRegClassID; // sparc float reg class
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else {
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//std::cerr << "TypeID: " << ty << "\n";
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assert(0 && "Cannot resolve register class for type");
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return 0;
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}
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if(isCCReg)
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return res + 2; // corresponidng condition code regiser
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else
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return res;
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}
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// To find the register class to which a specified register belongs
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//
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unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
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unsigned classId = 0;
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(void) getClassRegNum(unifiedRegNum, classId);
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return classId;
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}
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unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
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switch(regType) {
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case IntRegType: return IntRegClassID;
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case FPSingleRegType:
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case FPDoubleRegType: return FloatRegClassID;
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case IntCCRegType: return IntCCRegClassID;
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case FloatCCRegType: return FloatCCRegClassID;
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default:
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assert(0 && "Invalid register type in getRegClassIDOfRegType");
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return 0;
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}
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}
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//---------------------------------------------------------------------------
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// Suggests a register for the ret address in the RET machine instruction.
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// We always suggest %i7 by convention.
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
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LiveRangeInfo& LRI) const {
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assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
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// return address is always mapped to i7 so set it immediately
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RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
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SparcIntRegClass::i7));
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// Possible Optimization:
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// Instead of setting the color, we can suggest one. In that case,
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// we have to test later whether it received the suggested color.
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// In that case, a LR has to be created at the start of method.
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// It has to be done as follows (remove the setRegVal above):
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// MachineOperand & MO = RetMI->getOperand(0);
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// const Value *RetAddrVal = MO.getVRegValue();
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// assert( RetAddrVal && "LR for ret address must be created at start");
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// LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
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// RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
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// SparcIntRegOrdr::i7) );
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}
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//---------------------------------------------------------------------------
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// Suggests a register for the ret address in the JMPL/CALL machine instr.
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// Sparc ABI dictates that %o7 be used for this purpose.
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//---------------------------------------------------------------------------
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void
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UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
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LiveRangeInfo& LRI) const
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{
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CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
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const Value *RetAddrVal = argDesc->getReturnAddrReg();
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assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
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// A LR must already exist for the return address.
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LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
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assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
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unsigned RegClassID = RetAddrLR->getRegClass()->getID();
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RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
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}
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//---------------------------------------------------------------------------
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// This method will suggest colors to incoming args to a method.
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// According to the Sparc ABI, the first 6 incoming args are in
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// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
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// If the arg is passed on stack due to the lack of regs, NOTHING will be
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// done - it will be colored (or spilled) as a normal live range.
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
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LiveRangeInfo& LRI) const
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{
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// check if this is a varArgs function. needed for choosing regs.
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bool isVarArgs = isVarArgsFunction(Meth->getType());
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// for each argument. count INT and FP arguments separately.
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unsigned argNo=0, intArgNo=0, fpArgNo=0;
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for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
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I != E; ++I, ++argNo) {
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// get the LR of arg
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LiveRange *LR = LRI.getLiveRangeForValue(I);
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assert(LR && "No live range found for method arg");
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unsigned regType = getRegType(LR);
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unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
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int regNum = (regType == IntRegType)
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? regNumForIntArg(/*inCallee*/ true, isVarArgs,
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argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
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: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
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argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
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if(regNum != InvalidRegNum)
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LR->setSuggestedColor(regNum);
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}
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}
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//---------------------------------------------------------------------------
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// This method is called after graph coloring to move incoming args to
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// the correct hardware registers if they did not receive the correct
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// (suggested) color through graph coloring.
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
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LiveRangeInfo &LRI,
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AddedInstrns *FirstAI) const {
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// check if this is a varArgs function. needed for choosing regs.
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bool isVarArgs = isVarArgsFunction(Meth->getType());
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MachineInstr *AdMI;
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// for each argument
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// for each argument. count INT and FP arguments separately.
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unsigned argNo=0, intArgNo=0, fpArgNo=0;
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for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
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I != E; ++I, ++argNo) {
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// get the LR of arg
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LiveRange *LR = LRI.getLiveRangeForValue(I);
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assert( LR && "No live range found for method arg");
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unsigned regType = getRegType( LR );
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unsigned RegClassID = (LR->getRegClass())->getID();
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// Find whether this argument is coming in a register (if not, on stack)
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// Also find the correct register the argument must use (UniArgReg)
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//
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bool isArgInReg = false;
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unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
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unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
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int regNum = (regType == IntRegType)
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? regNumForIntArg(/*inCallee*/ true, isVarArgs,
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argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
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: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
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argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
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if(regNum != InvalidRegNum) {
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isArgInReg = true;
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UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
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}
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if( LR->hasColor() ) { // if this arg received a register
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unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
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// if LR received the correct color, nothing to do
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//
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if( UniLRReg == UniArgReg )
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continue;
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// We are here because the LR did not receive the suggested
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// but LR received another register.
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// Now we have to copy the %i reg (or stack pos of arg)
|
|
// to the register the LR was colored with.
|
|
|
|
// if the arg is coming in UniArgReg register, it MUST go into
|
|
// the UniLRReg register
|
|
//
|
|
if( isArgInReg ) {
|
|
if( regClassIDOfArgReg != RegClassID ) {
|
|
assert(0 && "This could should work but it is not tested yet");
|
|
|
|
// It is a variable argument call: the float reg must go in a %o reg.
|
|
// We have to move an int reg to a float reg via memory.
|
|
//
|
|
assert(isVarArgs &&
|
|
RegClassID == FloatRegClassID &&
|
|
regClassIDOfArgReg == IntRegClassID &&
|
|
"This should only be an Int register for an FP argument");
|
|
|
|
int TmpOff = MachineFunction::get(Meth).pushTempValue(target,
|
|
getSpilledRegSize(regType));
|
|
cpReg2MemMI(FirstAI->InstrnsBefore,
|
|
UniArgReg, getFramePointer(), TmpOff, IntRegType);
|
|
|
|
cpMem2RegMI(FirstAI->InstrnsBefore,
|
|
getFramePointer(), TmpOff, UniLRReg, regType);
|
|
}
|
|
else {
|
|
cpReg2RegMI(FirstAI->InstrnsBefore, UniArgReg, UniLRReg, regType);
|
|
}
|
|
}
|
|
else {
|
|
|
|
// Now the arg is coming on stack. Since the LR recieved a register,
|
|
// we just have to load the arg on stack into that register
|
|
//
|
|
const MachineFrameInfo& frameInfo = target.getFrameInfo();
|
|
int offsetFromFP =
|
|
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
|
|
argNo);
|
|
|
|
cpMem2RegMI(FirstAI->InstrnsBefore,
|
|
getFramePointer(), offsetFromFP, UniLRReg, regType);
|
|
}
|
|
|
|
} // if LR received a color
|
|
|
|
else {
|
|
|
|
// Now, the LR did not receive a color. But it has a stack offset for
|
|
// spilling.
|
|
// So, if the arg is coming in UniArgReg register, we can just move
|
|
// that on to the stack pos of LR
|
|
|
|
if( isArgInReg ) {
|
|
|
|
if( regClassIDOfArgReg != RegClassID ) {
|
|
assert(0 &&
|
|
"FP arguments to a varargs function should be explicitly "
|
|
"copied to/from int registers by instruction selection!");
|
|
|
|
// It must be a float arg for a variable argument call, which
|
|
// must come in a %o reg. Move the int reg to the stack.
|
|
//
|
|
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
|
|
"This should only be an Int register for an FP argument");
|
|
|
|
cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
|
|
getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
|
|
}
|
|
else {
|
|
cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
|
|
getFramePointer(), LR->getSpillOffFromFP(), regType);
|
|
}
|
|
}
|
|
|
|
else {
|
|
|
|
// Now the arg is coming on stack. Since the LR did NOT
|
|
// recieved a register as well, it is allocated a stack position. We
|
|
// can simply change the stack position of the LR. We can do this,
|
|
// since this method is called before any other method that makes
|
|
// uses of the stack pos of the LR (e.g., updateMachineInstr)
|
|
|
|
const MachineFrameInfo& frameInfo = target.getFrameInfo();
|
|
int offsetFromFP =
|
|
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
|
|
argNo);
|
|
|
|
LR->modifySpillOffFromFP( offsetFromFP );
|
|
}
|
|
|
|
}
|
|
|
|
} // for each incoming argument
|
|
|
|
}
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// This method is called before graph coloring to suggest colors to the
|
|
// outgoing call args and the return value of the call.
|
|
//---------------------------------------------------------------------------
|
|
void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
|
|
LiveRangeInfo& LRI) const {
|
|
assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
|
|
|
|
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
|
|
|
|
suggestReg4CallAddr(CallMI, LRI);
|
|
|
|
// First color the return value of the call instruction, if any.
|
|
// The return value will be in %o0 if the value is an integer type,
|
|
// or in %f0 if the value is a float type.
|
|
//
|
|
if (const Value *RetVal = argDesc->getReturnValue()) {
|
|
LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
|
|
assert(RetValLR && "No LR for return Value of call!");
|
|
|
|
unsigned RegClassID = RetValLR->getRegClass()->getID();
|
|
|
|
// now suggest a register depending on the register class of ret arg
|
|
if( RegClassID == IntRegClassID )
|
|
RetValLR->setSuggestedColor(SparcIntRegClass::o0);
|
|
else if (RegClassID == FloatRegClassID )
|
|
RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
|
|
else assert( 0 && "Unknown reg class for return value of call\n");
|
|
}
|
|
|
|
// Now suggest colors for arguments (operands) of the call instruction.
|
|
// Colors are suggested only if the arg number is smaller than the
|
|
// the number of registers allocated for argument passing.
|
|
// Now, go thru call args - implicit operands of the call MI
|
|
|
|
unsigned NumOfCallArgs = argDesc->getNumArgs();
|
|
|
|
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
|
|
i < NumOfCallArgs; ++i, ++argNo) {
|
|
|
|
const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
|
|
|
|
// get the LR of call operand (parameter)
|
|
LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
|
|
assert (LR && "Must have a LR for all arguments since "
|
|
"all args (even consts) must be defined before");
|
|
|
|
unsigned regType = getRegType( LR );
|
|
unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
|
|
|
|
// Choose a register for this arg depending on whether it is
|
|
// an INT or FP value. Here we ignore whether or not it is a
|
|
// varargs calls, because FP arguments will be explicitly copied
|
|
// to an integer Value and handled under (argCopy != NULL) below.
|
|
int regNum = (regType == IntRegType)
|
|
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
|
|
argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
|
|
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
|
|
argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
|
|
|
|
// If a register could be allocated, use it.
|
|
// If not, do NOTHING as this will be colored as a normal value.
|
|
if(regNum != InvalidRegNum)
|
|
LR->setSuggestedColor(regNum);
|
|
|
|
// Repeat for the second copy of the argument, which would be
|
|
// an FP argument being passed to a function with no prototype
|
|
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
|
|
if (argCopy != NULL)
|
|
{
|
|
assert(regType != IntRegType && argCopy->getType()->isInteger()
|
|
&& "Must be passing copy of FP argument in int register");
|
|
int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
|
|
argNo, intArgNo, fpArgNo-1,
|
|
regClassIDOfArgReg);
|
|
assert(copyRegNum != InvalidRegNum);
|
|
LiveRange *const copyLR = LRI.getLiveRangeForValue(argCopy);
|
|
copyLR->setSuggestedColor(copyRegNum);
|
|
}
|
|
|
|
} // for all call arguments
|
|
|
|
}
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Helper method for UltraSparcRegInfo::colorCallArgs().
|
|
//---------------------------------------------------------------------------
|
|
|
|
void
|
|
UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
|
|
AddedInstrns *CallAI,
|
|
PhyRegAlloc &PRA, LiveRange* LR,
|
|
unsigned regType, unsigned RegClassID,
|
|
int UniArgRegOrNone, unsigned int argNo,
|
|
std::vector<MachineInstr *>& AddedInstrnsBefore)
|
|
const
|
|
{
|
|
MachineInstr *AdMI;
|
|
bool isArgInReg = false;
|
|
unsigned UniArgReg = MAXINT; // unused unless initialized below
|
|
if (UniArgRegOrNone != InvalidRegNum)
|
|
{
|
|
isArgInReg = true;
|
|
UniArgReg = (unsigned) UniArgRegOrNone;
|
|
CallMI->insertUsedReg(UniArgReg); // mark the reg as used
|
|
}
|
|
|
|
if (LR->hasColor()) {
|
|
unsigned UniLRReg = getUnifiedRegNum(RegClassID, LR->getColor());
|
|
|
|
// if LR received the correct color, nothing to do
|
|
if( isArgInReg && UniArgReg == UniLRReg )
|
|
return;
|
|
|
|
// The LR is allocated to a register UniLRReg and must be copied
|
|
// to UniArgReg or to the stack slot.
|
|
//
|
|
if( isArgInReg ) {
|
|
// Copy UniLRReg to UniArgReg
|
|
cpReg2RegMI(AddedInstrnsBefore, UniLRReg, UniArgReg, regType);
|
|
}
|
|
else {
|
|
// Copy UniLRReg to the stack to pass the arg on stack.
|
|
const MachineFrameInfo& frameInfo = target.getFrameInfo();
|
|
int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
|
|
cpReg2MemMI(CallAI->InstrnsBefore,
|
|
UniLRReg, getStackPointer(), argOffset, regType);
|
|
}
|
|
|
|
} else { // LR is not colored (i.e., spilled)
|
|
|
|
if( isArgInReg ) {
|
|
// Insert a load instruction to load the LR to UniArgReg
|
|
cpMem2RegMI(AddedInstrnsBefore, getFramePointer(),
|
|
LR->getSpillOffFromFP(), UniArgReg, regType);
|
|
// Now add the instruction
|
|
}
|
|
|
|
else {
|
|
// Now, we have to pass the arg on stack. Since LR also did NOT
|
|
// receive a register we have to move an argument in memory to
|
|
// outgoing parameter on stack.
|
|
// Use TReg to load and store the value.
|
|
// Use TmpOff to save TReg, since that may have a live value.
|
|
//
|
|
int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
|
|
int TmpOff = PRA.MF.pushTempValue(target,
|
|
getSpilledRegSize(getRegType(LR)));
|
|
const MachineFrameInfo& frameInfo = target.getFrameInfo();
|
|
int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
|
|
|
|
MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
|
|
|
|
// Sequence:
|
|
// (1) Save TReg on stack
|
|
// (2) Load LR value into TReg from stack pos of LR
|
|
// (3) Store Treg on outgoing Arg pos on stack
|
|
// (4) Load the old value of TReg from stack to TReg (restore it)
|
|
//
|
|
// OPTIMIZE THIS:
|
|
// When reverse pointers in MahineInstr are introduced:
|
|
// Call PRA.getUnusedRegAtMI(....) to get an unused reg. Step 1 is
|
|
// needed only if this fails. Currently, we cannot call the
|
|
// above method since we cannot find LVSetBefore without the BB
|
|
//
|
|
// NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
|
|
// AddedInstrnsBefore since these instructions must not be reordered.
|
|
cpReg2MemMI(CallAI->InstrnsBefore,
|
|
TReg, getFramePointer(), TmpOff, regType);
|
|
cpMem2RegMI(CallAI->InstrnsBefore,
|
|
getFramePointer(), LR->getSpillOffFromFP(), TReg, regType);
|
|
cpReg2MemMI(CallAI->InstrnsBefore,
|
|
TReg, getStackPointer(), argOffset, regType);
|
|
cpMem2RegMI(CallAI->InstrnsBefore,
|
|
getFramePointer(), TmpOff, TReg, regType);
|
|
}
|
|
}
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
// After graph coloring, we have call this method to see whehter the return
|
|
// value and the call args received the correct colors. If not, we have
|
|
// to instert copy instructions.
|
|
//---------------------------------------------------------------------------
|
|
|
|
void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
|
|
LiveRangeInfo &LRI,
|
|
AddedInstrns *CallAI,
|
|
PhyRegAlloc &PRA,
|
|
const BasicBlock *BB) const {
|
|
|
|
assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
|
|
|
|
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
|
|
|
|
// First color the return value of the call.
|
|
// If there is a LR for the return value, it means this
|
|
// method returns a value
|
|
|
|
MachineInstr *AdMI;
|
|
|
|
const Value *RetVal = argDesc->getReturnValue();
|
|
|
|
if (RetVal) {
|
|
LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
|
|
|
|
if (!RetValLR) {
|
|
cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
|
|
assert(RetValLR && "ERR:No LR for non-void return value");
|
|
}
|
|
|
|
unsigned RegClassID = (RetValLR->getRegClass())->getID();
|
|
bool recvCorrectColor;
|
|
unsigned CorrectCol; // correct color for ret value
|
|
unsigned UniRetReg; // unified number for CorrectCol
|
|
|
|
if(RegClassID == IntRegClassID)
|
|
CorrectCol = SparcIntRegClass::o0;
|
|
else if(RegClassID == FloatRegClassID)
|
|
CorrectCol = SparcFloatRegClass::f0;
|
|
else {
|
|
assert( 0 && "Unknown RegClass");
|
|
return;
|
|
}
|
|
|
|
// convert to unified number
|
|
UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
|
|
|
|
// Mark the register as used by this instruction
|
|
CallMI->insertUsedReg(UniRetReg);
|
|
|
|
// if the LR received the correct color, NOTHING to do
|
|
recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
|
|
: false;
|
|
|
|
// if we didn't receive the correct color for some reason,
|
|
// put copy instruction
|
|
if( !recvCorrectColor ) {
|
|
|
|
unsigned regType = getRegType( RetValLR );
|
|
|
|
if( RetValLR->hasColor() ) {
|
|
|
|
unsigned UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
|
|
|
|
// the return value is coming in UniRetReg but has to go into
|
|
// the UniRetLRReg
|
|
|
|
cpReg2RegMI(CallAI->InstrnsAfter, UniRetReg, UniRetLRReg, regType);
|
|
|
|
} // if LR has color
|
|
else {
|
|
|
|
// if the LR did NOT receive a color, we have to move the return
|
|
// value coming in UniRetReg to the stack pos of spilled LR
|
|
|
|
cpReg2MemMI(CallAI->InstrnsAfter, UniRetReg,
|
|
getFramePointer(),RetValLR->getSpillOffFromFP(), regType);
|
|
}
|
|
|
|
} // the LR didn't receive the suggested color
|
|
|
|
} // if there a return value
|
|
|
|
|
|
//-------------------------------------------
|
|
// Now color all args of the call instruction
|
|
//-------------------------------------------
|
|
|
|
std::vector<MachineInstr *> AddedInstrnsBefore;
|
|
|
|
unsigned NumOfCallArgs = argDesc->getNumArgs();
|
|
|
|
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
|
|
i < NumOfCallArgs; ++i, ++argNo) {
|
|
|
|
const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
|
|
|
|
// get the LR of call operand (parameter)
|
|
LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
|
|
|
|
unsigned RegClassID = getRegClassIDOfValue( CallArg);
|
|
unsigned regType = getRegType( RegClassID, CallArg->getType() );
|
|
|
|
// Find whether this argument is coming in a register (if not, on stack)
|
|
// Also find the correct register the argument must use (UniArgReg)
|
|
//
|
|
bool isArgInReg = false;
|
|
unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
|
|
unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg
|
|
|
|
// Find the register that must be used for this arg, depending on
|
|
// whether it is an INT or FP value. Here we ignore whether or not it
|
|
// is a varargs calls, because FP arguments will be explicitly copied
|
|
// to an integer Value and handled under (argCopy != NULL) below.
|
|
int regNum = (regType == IntRegType)
|
|
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
|
|
argNo, intArgNo++, fpArgNo, regClassIDOfArgReg)
|
|
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
|
|
argNo, intArgNo, fpArgNo++, regClassIDOfArgReg);
|
|
|
|
if(regNum != InvalidRegNum) {
|
|
isArgInReg = true;
|
|
UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
|
|
assert(regClassIDOfArgReg == RegClassID &&
|
|
"Moving values between reg classes must happen during selection");
|
|
}
|
|
|
|
// not possible to have a null LR since all args (even consts)
|
|
// must be defined before
|
|
if (!LR) {
|
|
cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
|
|
assert(LR && "NO LR for call arg");
|
|
}
|
|
|
|
InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
|
|
UniArgReg, argNo, AddedInstrnsBefore);
|
|
|
|
// Repeat for the second copy of the argument, which would be
|
|
// an FP argument being passed to a function with no prototype.
|
|
// It may either be passed as a copy in an integer register
|
|
// (in argCopy), or on the stack (useStackSlot).
|
|
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
|
|
if (argCopy != NULL)
|
|
{
|
|
assert(regType != IntRegType && argCopy->getType()->isInteger()
|
|
&& "Must be passing copy of FP argument in int register");
|
|
|
|
unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
|
|
unsigned copyRegType = getRegType(copyRegClassID, argCopy->getType());
|
|
|
|
int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
|
|
argNo, intArgNo, fpArgNo-1,
|
|
regClassIDOfArgReg);
|
|
assert(copyRegNum != InvalidRegNum);
|
|
assert(regClassIDOfArgReg == copyRegClassID &&
|
|
"Moving values between reg classes must happen during selection");
|
|
|
|
InitializeOutgoingArg(CallMI, CallAI, PRA,
|
|
LRI.getLiveRangeForValue(argCopy), copyRegType,
|
|
copyRegClassID, copyRegNum, argNo,
|
|
AddedInstrnsBefore);
|
|
}
|
|
|
|
if (regNum != InvalidRegNum &&
|
|
argDesc->getArgInfo(i).usesStackSlot())
|
|
{
|
|
// Pass the argument via the stack in addition to regNum
|
|
assert(regType != IntRegType && "Passing an integer arg. twice?");
|
|
assert(!argCopy && "Passing FP arg in FP reg, INT reg, and stack?");
|
|
InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
|
|
InvalidRegNum, argNo, AddedInstrnsBefore);
|
|
}
|
|
} // for each parameter in call instruction
|
|
|
|
// If we added any instruction before the call instruction, verify
|
|
// that they are in the proper order and if not, reorder them
|
|
//
|
|
std::vector<MachineInstr *> ReorderedVec;
|
|
if (!AddedInstrnsBefore.empty()) {
|
|
|
|
if (DEBUG_RA) {
|
|
cerr << "\nCalling reorder with instrns: \n";
|
|
for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
|
|
cerr << *(AddedInstrnsBefore[i]);
|
|
}
|
|
|
|
OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
|
|
assert(ReorderedVec.size() >= AddedInstrnsBefore.size()
|
|
&& "Dropped some instructions when reordering!");
|
|
|
|
if (DEBUG_RA) {
|
|
cerr << "\nAfter reordering instrns: \n";
|
|
for(unsigned i = 0; i < ReorderedVec.size(); i++)
|
|
cerr << *ReorderedVec[i];
|
|
}
|
|
}
|
|
|
|
// Now insert caller saving code for this call instruction
|
|
//
|
|
insertCallerSavingCode(CallAI->InstrnsBefore, CallAI->InstrnsAfter,
|
|
CallMI, BB, PRA);
|
|
|
|
// Then insert the final reordered code for the call arguments.
|
|
//
|
|
for(unsigned i=0; i < ReorderedVec.size(); i++)
|
|
CallAI->InstrnsBefore.push_back( ReorderedVec[i] );
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
// This method is called for an LLVM return instruction to identify which
|
|
// values will be returned from this method and to suggest colors.
|
|
//---------------------------------------------------------------------------
|
|
void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
|
|
LiveRangeInfo &LRI) const {
|
|
|
|
assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
|
|
|
|
suggestReg4RetAddr(RetMI, LRI);
|
|
|
|
// if there is an implicit ref, that has to be the ret value
|
|
if( RetMI->getNumImplicitRefs() > 0 ) {
|
|
|
|
// The first implicit operand is the return value of a return instr
|
|
const Value *RetVal = RetMI->getImplicitRef(0);
|
|
|
|
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
|
|
|
|
if (!LR) {
|
|
cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
|
|
assert(0 && "No LR for return value of non-void method");
|
|
}
|
|
|
|
unsigned RegClassID = (LR->getRegClass())->getID();
|
|
|
|
if (RegClassID == IntRegClassID)
|
|
LR->setSuggestedColor(SparcIntRegClass::i0);
|
|
else if (RegClassID == FloatRegClassID)
|
|
LR->setSuggestedColor(SparcFloatRegClass::f0);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Colors the return value of a method to %i0 or %f0, if possible. If it is
|
|
// not possilbe to directly color the LR, insert a copy instruction to move
|
|
// the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
|
|
// have to put a load instruction.
|
|
//---------------------------------------------------------------------------
|
|
void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
|
|
LiveRangeInfo &LRI,
|
|
AddedInstrns *RetAI) const {
|
|
|
|
assert((target.getInstrInfo()).isReturn( RetMI->getOpCode()));
|
|
|
|
// if there is an implicit ref, that has to be the ret value
|
|
if(RetMI->getNumImplicitRefs() > 0) {
|
|
|
|
// The first implicit operand is the return value of a return instr
|
|
const Value *RetVal = RetMI->getImplicitRef(0);
|
|
|
|
LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
|
|
|
|
if (!LR) {
|
|
cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
|
|
// assert( LR && "No LR for return value of non-void method");
|
|
return;
|
|
}
|
|
|
|
unsigned RegClassID = getRegClassIDOfValue(RetVal);
|
|
unsigned regType = getRegType( RetVal );
|
|
|
|
unsigned CorrectCol;
|
|
if(RegClassID == IntRegClassID)
|
|
CorrectCol = SparcIntRegClass::i0;
|
|
else if(RegClassID == FloatRegClassID)
|
|
CorrectCol = SparcFloatRegClass::f0;
|
|
else {
|
|
assert (0 && "Unknown RegClass");
|
|
return;
|
|
}
|
|
|
|
// convert to unified number
|
|
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
|
|
|
|
// Mark the register as used by this instruction
|
|
RetMI->insertUsedReg(UniRetReg);
|
|
|
|
// if the LR received the correct color, NOTHING to do
|
|
|
|
if (LR->hasColor() && LR->getColor() == CorrectCol)
|
|
return;
|
|
|
|
if (LR->hasColor()) {
|
|
|
|
// We are here because the LR was allocted a regiter
|
|
// It may be the suggested register or not
|
|
|
|
// copy the LR of retun value to i0 or f0
|
|
|
|
unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
|
|
|
|
// the LR received UniLRReg but must be colored with UniRetReg
|
|
// to pass as the return value
|
|
cpReg2RegMI(RetAI->InstrnsBefore, UniLRReg, UniRetReg, regType);
|
|
}
|
|
else { // if the LR is spilled
|
|
cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
|
|
LR->getSpillOffFromFP(), UniRetReg, regType);
|
|
cerr << "\nCopied the return value from stack\n";
|
|
}
|
|
|
|
} // if there is a return value
|
|
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Check if a specified register type needs a scratch register to be
|
|
// copied to/from memory. If it does, the reg. type that must be used
|
|
// for scratch registers is returned in scratchRegType.
|
|
//
|
|
// Only the int CC register needs such a scratch register.
|
|
// The FP CC registers can (and must) be copied directly to/from memory.
|
|
//---------------------------------------------------------------------------
|
|
|
|
bool
|
|
UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
|
|
int& scratchRegType) const
|
|
{
|
|
if (RegType == IntCCRegType)
|
|
{
|
|
scratchRegType = IntRegType;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Copy from a register to register. Register number must be the unified
|
|
// register number.
|
|
//---------------------------------------------------------------------------
|
|
|
|
void
|
|
UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
|
|
unsigned SrcReg,
|
|
unsigned DestReg,
|
|
int RegType) const {
|
|
assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
|
|
"Invalid Register");
|
|
|
|
MachineInstr * MI = NULL;
|
|
|
|
switch( RegType ) {
|
|
|
|
case IntCCRegType:
|
|
if (getRegType(DestReg) == IntRegType)
|
|
{ // copy intCC reg to int reg
|
|
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
|
|
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
|
|
}
|
|
else
|
|
{ // copy int reg to intCC reg
|
|
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
|
|
assert(getRegType(SrcReg) == IntRegType
|
|
&& "Can only copy CC reg to/from integer reg");
|
|
MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
|
|
}
|
|
break;
|
|
|
|
case FloatCCRegType:
|
|
assert(0 && "Cannot copy FPCC register to any other register");
|
|
break;
|
|
|
|
case IntRegType:
|
|
MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg);
|
|
break;
|
|
|
|
case FPSingleRegType:
|
|
MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg);
|
|
break;
|
|
|
|
case FPDoubleRegType:
|
|
MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg);
|
|
break;
|
|
|
|
default:
|
|
assert(0 && "Unknown RegType");
|
|
break;
|
|
}
|
|
|
|
if (MI)
|
|
mvec.push_back(MI);
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Copy from a register to memory (i.e., Store). Register number must
|
|
// be the unified register number
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
void
|
|
UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
|
|
unsigned SrcReg,
|
|
unsigned DestPtrReg,
|
|
int Offset, int RegType,
|
|
int scratchReg) const {
|
|
MachineInstr * MI = NULL;
|
|
switch( RegType ) {
|
|
case IntRegType:
|
|
assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
|
|
MI = new MachineInstr(STX, 3);
|
|
MI->SetMachineOperandReg(0, SrcReg);
|
|
MI->SetMachineOperandReg(1, DestPtrReg);
|
|
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
case FPSingleRegType:
|
|
assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
|
|
MI = new MachineInstr(ST, 3);
|
|
MI->SetMachineOperandReg(0, SrcReg);
|
|
MI->SetMachineOperandReg(1, DestPtrReg);
|
|
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
case FPDoubleRegType:
|
|
assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
|
|
MI = new MachineInstr(STD, 3);
|
|
MI->SetMachineOperandReg(0, SrcReg);
|
|
MI->SetMachineOperandReg(1, DestPtrReg);
|
|
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
case IntCCRegType:
|
|
assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
|
|
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
|
|
|
|
// Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
|
|
MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
|
|
mvec.push_back(MI);
|
|
|
|
cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
|
|
break;
|
|
|
|
case FloatCCRegType:
|
|
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
|
|
assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
|
|
MI = new MachineInstr(STXFSR, 3);
|
|
MI->SetMachineOperandReg(0, SrcReg);
|
|
MI->SetMachineOperandReg(1, DestPtrReg);
|
|
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
default:
|
|
assert(0 && "Unknown RegType in cpReg2MemMI");
|
|
}
|
|
}
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Copy from memory to a reg (i.e., Load) Register number must be the unified
|
|
// register number
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
void
|
|
UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
|
|
unsigned SrcPtrReg,
|
|
int Offset,
|
|
unsigned DestReg,
|
|
int RegType,
|
|
int scratchReg) const {
|
|
MachineInstr * MI = NULL;
|
|
switch (RegType) {
|
|
case IntRegType:
|
|
assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
|
|
MI = new MachineInstr(LDX, 3);
|
|
MI->SetMachineOperandReg(0, SrcPtrReg);
|
|
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
MI->SetMachineOperandReg(2, DestReg, true);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
case FPSingleRegType:
|
|
assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
|
|
MI = new MachineInstr(LD, 3);
|
|
MI->SetMachineOperandReg(0, SrcPtrReg);
|
|
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
MI->SetMachineOperandReg(2, DestReg, true);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
case FPDoubleRegType:
|
|
assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
|
|
MI = new MachineInstr(LDD, 3);
|
|
MI->SetMachineOperandReg(0, SrcPtrReg);
|
|
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
MI->SetMachineOperandReg(2, DestReg, true);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
case IntCCRegType:
|
|
assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
|
|
assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
|
|
cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
|
|
|
|
// Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
|
|
MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
|
|
mvec.push_back(MI);
|
|
|
|
break;
|
|
|
|
case FloatCCRegType:
|
|
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
|
|
assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
|
|
MI = new MachineInstr(LDXFSR, 3);
|
|
MI->SetMachineOperandReg(0, SrcPtrReg);
|
|
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
|
|
(int64_t) Offset);
|
|
MI->SetMachineOperandReg(2, DestReg, true);
|
|
mvec.push_back(MI);
|
|
break;
|
|
|
|
default:
|
|
assert(0 && "Unknown RegType in cpMem2RegMI");
|
|
}
|
|
}
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Generate a copy instruction to copy a value to another. Temporarily
|
|
// used by PhiElimination code.
|
|
//---------------------------------------------------------------------------
|
|
|
|
|
|
void
|
|
UltraSparcRegInfo::cpValue2Value(Value *Src,
|
|
Value *Dest,
|
|
vector<MachineInstr*>& mvec) const {
|
|
int RegType = getRegType( Src );
|
|
|
|
assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
|
|
|
|
MachineInstr * MI = NULL;
|
|
|
|
switch( RegType ) {
|
|
case IntRegType:
|
|
MI = new MachineInstr(ADD, 3);
|
|
MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
|
|
MI->SetMachineOperandReg(1, getZeroRegNum());
|
|
MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true);
|
|
break;
|
|
|
|
case FPSingleRegType:
|
|
MI = new MachineInstr(FMOVS, 2);
|
|
MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
|
|
MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
|
|
break;
|
|
|
|
|
|
case FPDoubleRegType:
|
|
MI = new MachineInstr(FMOVD, 2);
|
|
MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
|
|
MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
|
|
break;
|
|
|
|
default:
|
|
assert(0 && "Unknow RegType in CpValu2Value");
|
|
}
|
|
|
|
mvec.push_back(MI);
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
// This method inserts caller saving/restoring instructons before/after
|
|
// a call machine instruction. The caller saving/restoring instructions are
|
|
// inserted like:
|
|
//
|
|
// ** caller saving instructions
|
|
// other instructions inserted for the call by ColorCallArg
|
|
// CALL instruction
|
|
// other instructions inserted for the call ColorCallArg
|
|
// ** caller restoring instructions
|
|
//
|
|
//----------------------------------------------------------------------------
|
|
|
|
|
|
void
|
|
UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
|
|
vector<MachineInstr*>& instrnsAfter,
|
|
MachineInstr *CallMI,
|
|
const BasicBlock *BB,
|
|
PhyRegAlloc &PRA) const
|
|
{
|
|
assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
|
|
|
|
// has set to record which registers were saved/restored
|
|
//
|
|
hash_set<unsigned> PushedRegSet;
|
|
|
|
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
|
|
|
|
// Now find the LR of the return value of the call
|
|
// The last *implicit operand* is the return value of a call
|
|
// Insert it to to he PushedRegSet since we must not save that register
|
|
// and restore it after the call.
|
|
// We do this because, we look at the LV set *after* the instruction
|
|
// to determine, which LRs must be saved across calls. The return value
|
|
// of the call is live in this set - but we must not save/restore it.
|
|
|
|
const Value *RetVal = argDesc->getReturnValue();
|
|
|
|
if (RetVal) {
|
|
LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
|
|
assert(RetValLR && "No LR for RetValue of call");
|
|
|
|
if (RetValLR->hasColor())
|
|
PushedRegSet.insert(
|
|
getUnifiedRegNum((RetValLR->getRegClass())->getID(),
|
|
RetValLR->getColor() ) );
|
|
}
|
|
|
|
const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
|
|
ValueSet::const_iterator LIt = LVSetAft.begin();
|
|
|
|
// for each live var in live variable set after machine inst
|
|
for( ; LIt != LVSetAft.end(); ++LIt) {
|
|
|
|
// get the live range corresponding to live var
|
|
LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
|
|
|
|
// LR can be null if it is a const since a const
|
|
// doesn't have a dominating def - see Assumptions above
|
|
if( LR ) {
|
|
|
|
if( LR->hasColor() ) {
|
|
|
|
unsigned RCID = (LR->getRegClass())->getID();
|
|
unsigned Color = LR->getColor();
|
|
|
|
if ( isRegVolatile(RCID, Color) ) {
|
|
|
|
// if the value is in both LV sets (i.e., live before and after
|
|
// the call machine instruction)
|
|
|
|
unsigned Reg = getUnifiedRegNum(RCID, Color);
|
|
|
|
if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
|
|
|
|
// if we haven't already pushed that register
|
|
|
|
unsigned RegType = getRegType( LR );
|
|
|
|
// Now get two instructions - to push on stack and pop from stack
|
|
// and add them to InstrnsBefore and InstrnsAfter of the
|
|
// call instruction
|
|
//
|
|
int StackOff = PRA.MF.pushTempValue(target,
|
|
getSpilledRegSize(RegType));
|
|
|
|
vector<MachineInstr*> AdIBef, AdIAft;
|
|
|
|
//---- Insert code for pushing the reg on stack ----------
|
|
|
|
// We may need a scratch register to copy the saved value
|
|
// to/from memory. This may itself have to insert code to
|
|
// free up a scratch register. Any such code should go before
|
|
// the save code.
|
|
int scratchRegType = -1;
|
|
int scratchReg = -1;
|
|
if (regTypeNeedsScratchReg(RegType, scratchRegType))
|
|
{ // Find a register not live in the LVSet before CallMI
|
|
const ValueSet &LVSetBef =
|
|
PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
|
|
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
|
|
CallMI, AdIBef, AdIAft);
|
|
assert(scratchReg != getInvalidRegNum());
|
|
CallMI->insertUsedReg(scratchReg);
|
|
}
|
|
|
|
if (AdIBef.size() > 0)
|
|
instrnsBefore.insert(instrnsBefore.end(),
|
|
AdIBef.begin(), AdIBef.end());
|
|
|
|
cpReg2MemMI(instrnsBefore, Reg,getFramePointer(),StackOff,RegType,
|
|
scratchReg);
|
|
|
|
if (AdIAft.size() > 0)
|
|
instrnsBefore.insert(instrnsBefore.end(),
|
|
AdIAft.begin(), AdIAft.end());
|
|
|
|
//---- Insert code for popping the reg from the stack ----------
|
|
|
|
// We may need a scratch register to copy the saved value
|
|
// from memory. This may itself have to insert code to
|
|
// free up a scratch register. Any such code should go
|
|
// after the save code.
|
|
//
|
|
scratchRegType = -1;
|
|
scratchReg = -1;
|
|
if (regTypeNeedsScratchReg(RegType, scratchRegType))
|
|
{ // Find a register not live in the LVSet after CallMI
|
|
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
|
|
CallMI, AdIBef, AdIAft);
|
|
assert(scratchReg != getInvalidRegNum());
|
|
CallMI->insertUsedReg(scratchReg);
|
|
}
|
|
|
|
if (AdIBef.size() > 0)
|
|
instrnsAfter.insert(instrnsAfter.end(),
|
|
AdIBef.begin(), AdIBef.end());
|
|
|
|
cpMem2RegMI(instrnsAfter, getFramePointer(), StackOff,Reg,RegType,
|
|
scratchReg);
|
|
|
|
if (AdIAft.size() > 0)
|
|
instrnsAfter.insert(instrnsAfter.end(),
|
|
AdIAft.begin(), AdIAft.end());
|
|
|
|
PushedRegSet.insert(Reg);
|
|
|
|
if(DEBUG_RA) {
|
|
cerr << "\nFor call inst:" << *CallMI;
|
|
cerr << " -inserted caller saving instrs: Before:\n\t ";
|
|
for_each(instrnsBefore.begin(), instrnsBefore.end(),
|
|
std::mem_fun(&MachineInstr::dump));
|
|
cerr << " -and After:\n\t ";
|
|
for_each(instrnsAfter.begin(), instrnsAfter.end(),
|
|
std::mem_fun(&MachineInstr::dump));
|
|
}
|
|
} // if not already pushed
|
|
|
|
} // if LR has a volatile color
|
|
|
|
} // if LR has color
|
|
|
|
} // if there is a LR for Var
|
|
|
|
} // for each value in the LV set after instruction
|
|
}
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Print the register assigned to a LR
|
|
//---------------------------------------------------------------------------
|
|
|
|
void UltraSparcRegInfo::printReg(const LiveRange *LR) {
|
|
unsigned RegClassID = (LR->getRegClass())->getID();
|
|
cerr << " *Node " << (LR->getUserIGNode())->getIndex();
|
|
|
|
if (!LR->hasColor()) {
|
|
cerr << " - could not find a color\n";
|
|
return;
|
|
}
|
|
|
|
// if a color is found
|
|
|
|
cerr << " colored with color "<< LR->getColor();
|
|
|
|
if (RegClassID == IntRegClassID) {
|
|
cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
|
|
|
|
} else if (RegClassID == FloatRegClassID) {
|
|
cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
|
|
if( LR->getType() == Type::DoubleTy)
|
|
cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
|
|
cerr << "]\n";
|
|
}
|
|
}
|
|
|
|
//---------------------------------------------------------------------------
|
|
// This method examines instructions inserted by RegAlloc code before a
|
|
// machine instruction to detect invalid orders that destroy values before
|
|
// they are used. If it detects such conditions, it reorders the instructions.
|
|
//
|
|
// The unordered instructions come in the UnordVec. These instructions are
|
|
// instructions inserted by RegAlloc. All such instruction MUST have
|
|
// their USES BEFORE THE DEFS after reordering.
|
|
//
|
|
// The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
|
|
// this method is called.
|
|
//
|
|
// This method uses two vectors for efficiency in accessing
|
|
//
|
|
// Since instructions are inserted in RegAlloc, this assumes that the
|
|
// first operand is the source reg and the last operand is the dest reg.
|
|
// It also does not consider operands that are both use and def.
|
|
//
|
|
// All the uses are before THE def to a register
|
|
//---------------------------------------------------------------------------
|
|
|
|
void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr*> &UnordVec,
|
|
std::vector<MachineInstr*> &OrdVec,
|
|
PhyRegAlloc &PRA) const{
|
|
|
|
/*
|
|
Problem: We can have instructions inserted by RegAlloc like
|
|
1. add %ox %g0 %oy
|
|
2. add %oy %g0 %oz, where z!=x or z==x
|
|
|
|
This is wrong since %oy used by 2 is overwritten by 1
|
|
|
|
Solution:
|
|
We re-order the instructions so that the uses are before the defs
|
|
|
|
Algorithm:
|
|
|
|
do
|
|
for each instruction 'DefInst' in the UnOrdVec
|
|
for each instruction 'UseInst' that follows the DefInst
|
|
if the reg defined by DefInst is used by UseInst
|
|
mark DefInst as not movable in this iteration
|
|
If DefInst is not marked as not-movable, move DefInst to OrdVec
|
|
while all instructions in DefInst are moved to OrdVec
|
|
|
|
For moving, we call the move2OrdVec(). It checks whether there is a def
|
|
in it for the uses in the instruction to be added to OrdVec. If there
|
|
are no preceding defs, it just appends the instruction. If there is a
|
|
preceding def, it puts two instructions to save the reg on stack before
|
|
the load and puts a restore at use.
|
|
|
|
*/
|
|
|
|
bool CouldMoveAll;
|
|
bool DebugPrint = false;
|
|
|
|
do {
|
|
CouldMoveAll = true;
|
|
std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
|
|
|
|
for( ; DefIt != UnordVec.end(); ++DefIt ) {
|
|
|
|
// for each instruction in the UnordVec do ...
|
|
|
|
MachineInstr *DefInst = *DefIt;
|
|
|
|
if( DefInst == NULL) continue;
|
|
|
|
//cerr << "\nInst in UnordVec = " << *DefInst;
|
|
|
|
// last operand is the def (unless for a store which has no def reg)
|
|
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
|
|
|
|
if (DefOp.opIsDef() &&
|
|
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
|
|
|
// If the operand in DefInst is a def ...
|
|
bool DefEqUse = false;
|
|
|
|
std::vector<MachineInstr *>::iterator UseIt = DefIt;
|
|
UseIt++;
|
|
|
|
for( ; UseIt != UnordVec.end(); ++UseIt ) {
|
|
|
|
MachineInstr *UseInst = *UseIt;
|
|
if( UseInst == NULL) continue;
|
|
|
|
// for each inst (UseInst) that is below the DefInst do ...
|
|
MachineOperand& UseOp = UseInst->getOperand(0);
|
|
|
|
if (!UseOp.opIsDef() &&
|
|
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
|
|
|
// if use is a register ...
|
|
|
|
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
|
|
|
|
// if Def and this use are the same, it means that this use
|
|
// is destroyed by a def before it is used
|
|
|
|
// cerr << "\nCouldn't move " << *DefInst;
|
|
|
|
DefEqUse = true;
|
|
CouldMoveAll = false;
|
|
DebugPrint = true;
|
|
break;
|
|
} // if two registers are equal
|
|
|
|
} // if use is a register
|
|
|
|
}// for all use instructions
|
|
|
|
if( ! DefEqUse ) {
|
|
|
|
// after examining all the instructions that follow the DefInst
|
|
// if there are no dependencies, we can move it to the OrdVec
|
|
|
|
// cerr << "Moved to Ord: " << *DefInst;
|
|
|
|
moveInst2OrdVec(OrdVec, DefInst, PRA);
|
|
|
|
//OrdVec.push_back(DefInst);
|
|
|
|
// mark the pos of DefInst with NULL to indicate that it is
|
|
// empty
|
|
*DefIt = NULL;
|
|
}
|
|
|
|
} // if Def is a machine register
|
|
|
|
} // for all instructions in the UnordVec
|
|
|
|
|
|
} while(!CouldMoveAll);
|
|
|
|
if (DebugPrint && DEBUG_RA) {
|
|
cerr << "\nAdded instructions were reordered to:\n";
|
|
for(unsigned int i=0; i < OrdVec.size(); i++)
|
|
cerr << *(OrdVec[i]);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
|
|
MachineInstr *UnordInst,
|
|
PhyRegAlloc &PRA) const {
|
|
MachineOperand& UseOp = UnordInst->getOperand(0);
|
|
|
|
if (!UseOp.opIsDef() &&
|
|
UseOp.getType() == MachineOperand::MO_MachineRegister) {
|
|
|
|
// for the use of UnordInst, see whether there is a defining instr
|
|
// before in the OrdVec
|
|
bool DefEqUse = false;
|
|
|
|
std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
|
|
|
|
for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
|
|
|
|
MachineInstr *OrdInst = *OrdIt ;
|
|
|
|
MachineOperand& DefOp =
|
|
OrdInst->getOperand(OrdInst->getNumOperands()-1);
|
|
|
|
if( DefOp.opIsDef() &&
|
|
DefOp.getType() == MachineOperand::MO_MachineRegister) {
|
|
|
|
//cerr << "\nDefining Ord Inst: " << *OrdInst;
|
|
|
|
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
|
|
|
|
// we are here because there is a preceding def in the OrdVec
|
|
// for the use in this intr we are going to insert. This
|
|
// happened because the original code was like:
|
|
// 1. add %ox %g0 %oy
|
|
// 2. add %oy %g0 %ox
|
|
// In Round1, we added 2 to OrdVec but 1 remained in UnordVec
|
|
// Now we are processing %ox of 1.
|
|
// We have to
|
|
|
|
int UReg = DefOp.getMachineRegNum();
|
|
int RegType = getRegType(UReg);
|
|
MachineInstr *AdIBef, *AdIAft;
|
|
|
|
const int StackOff = PRA.MF.pushTempValue(target,
|
|
getSpilledRegSize(RegType));
|
|
|
|
// Save the UReg (%ox) on stack before it's destroyed
|
|
vector<MachineInstr*> mvec;
|
|
cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
|
|
for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
|
|
OrdIt = OrdVec.insert(OrdIt, *MI);
|
|
++OrdIt; // OrdIt must still point to current instr we processed
|
|
}
|
|
|
|
// Load directly into DReg (%oy)
|
|
MachineOperand& DOp=
|
|
(UnordInst->getOperand(UnordInst->getNumOperands()-1));
|
|
assert(DOp.opIsDef() && "Last operand is not the def");
|
|
const int DReg = DOp.getMachineRegNum();
|
|
|
|
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
|
|
|
|
if( DEBUG_RA ) {
|
|
cerr << "\nFixed CIRCULAR references by reordering:";
|
|
cerr << "\nBefore CIRCULAR Reordering:\n";
|
|
cerr << *UnordInst;
|
|
cerr << *OrdInst;
|
|
|
|
cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
|
|
for(unsigned i=0; i < OrdVec.size(); i++)
|
|
cerr << *(OrdVec[i]);
|
|
}
|
|
|
|
// Do not copy the UseInst to OrdVec
|
|
DefEqUse = true;
|
|
break;
|
|
|
|
}// if two registers are equal
|
|
|
|
} // if Def is a register
|
|
|
|
} // for each instr in OrdVec
|
|
|
|
if(!DefEqUse) {
|
|
|
|
// We didn't find a def in the OrdVec, so just append this inst
|
|
OrdVec.push_back( UnordInst );
|
|
//cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
|
|
}
|
|
|
|
}// if the operand in UnordInst is a use
|
|
}
|