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0332323ab6
Set the transform bar at 2 divisions because the fastest current x86 FP divider circuit is in SandyBridge / Haswell at 10 cycle latency (best case) relative to a 5 cycle multiplier. So that's the worst case for this transform (no latency win), but multiplies are obviously pipelined while divisions are not, so there's still a big throughput win which we would expect to show up in typical FP code. These are the sequences I'm comparing: divss %xmm2, %xmm0 mulss %xmm1, %xmm0 divss %xmm2, %xmm0 Becomes: movss LCPI0_0(%rip), %xmm3 ## xmm3 = mem[0],zero,zero,zero divss %xmm2, %xmm3 mulss %xmm3, %xmm0 mulss %xmm1, %xmm0 mulss %xmm3, %xmm0 [Ignore for the moment that we don't optimize the chain of 3 multiplies into 2 independent fmuls followed by 1 dependent fmul...this is the DAG version of: https://llvm.org/bugs/show_bug.cgi?id=21768 ...if we fix that, then the transform becomes even more profitable on all targets.] Differential Revision: http://reviews.llvm.org/D8941 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235012 91177308-0d34-0410-b5e6-96231b3b80d8
1087 lines
41 KiB
C++
1087 lines
41 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
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#define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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namespace llvm {
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class X86Subtarget;
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class X86TargetMachine;
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// Bit scan forward.
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BSF,
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/// Bit scan reverse.
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BSR,
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/// Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// Bitwise logical AND of floating point values. This corresponds
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/// to X86::ANDPS or X86::ANDPD.
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FAND,
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/// Bitwise logical OR of floating point values. This corresponds
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/// to X86::ORPS or X86::ORPD.
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FOR,
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/// Bitwise logical XOR of floating point values. This corresponds
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/// to X86::XORPS or X86::XORPD.
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FXOR,
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/// Bitwise logical ANDNOT of floating point values. This
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/// corresponds to X86::ANDNPS or X86::ANDNPD.
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FANDN,
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/// Bitwise logical right shift of floating point values. This
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/// corresponds to X86::PSRLDQ.
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FSRL,
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/// These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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CALL,
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/// This operation implements the lowering for readcyclecounter
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RDTSC_DAG,
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/// X86 Read Time-Stamp Counter and Processor ID.
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RDTSCP_DAG,
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/// X86 Read Performance Monitoring Counters.
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RDPMC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, COMI, UCOMI,
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/// X86 bit-test instructions.
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BT,
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/// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
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/// operand, usually produced by a CMP instruction.
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SETCC,
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/// X86 Select
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SELECT,
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// Same as SETCC except it's materialized with a sbb and the value is all
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// one's or all zero's.
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SETCC_CARRY, // R = carry_bit ? ~0 : 0
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/// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
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/// Operands are two FP values to compare; result is a mask of
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/// 0s or 1s. Generally DTRT for C/C++ with NaNs.
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FSETCC,
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/// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
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/// result in an integer GPR. Needs masking for scalar result.
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FGETSIGNx86,
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/// X86 conditional moves. Operand 0 and operand 1 are the two values
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/// to select from. Operand 2 is the condition code, and operand 3 is the
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/// flag operand produced by a CMP or TEST instruction. It also writes a
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/// flag result.
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CMOV,
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/// X86 conditional branches. Operand 0 is the chain operand, operand 1
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/// is the block to branch if condition is true, operand 2 is the
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/// condition code, and operand 3 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 0 is the chain operand, operand
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/// 1 is the number of bytes of stack to pop.
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RET_FLAG,
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/// Repeat fill, corresponds to X86::REP_STOSx.
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REP_STOS,
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/// Repeat move, corresponds to X86::REP_MOVSx.
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REP_MOVS,
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/// On Darwin, this node represents the result of the popl
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// A wrapper node for TargetConstantPool,
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/// TargetExternalSymbol, and TargetGlobalAddress.
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Wrapper,
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/// Special wrapper used under X86-64 PIC mode for RIP
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/// relative displacements.
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WrapperRIP,
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/// Copies a 64-bit value from the low word of an XMM vector
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/// to an MMX vector. If you think this is too close to the previous
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/// mnemonic, so do I; blame Intel.
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MOVDQ2Q,
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/// Copies a 32-bit value from the low word of a MMX
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/// vector to a GPR.
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MMX_MOVD2W,
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/// Copies a GPR into the low 32-bit word of a MMX vector
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/// and zero out the high word.
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MMX_MOVW2D,
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/// Extract an 8-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRB.
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PEXTRB,
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/// Extract a 16-bit value from a vector and zero extend it to
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/// i32, corresponds to X86::PEXTRW.
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PEXTRW,
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/// Insert any element of a 4 x float vector into any element
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/// of a destination 4 x floatvector.
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INSERTPS,
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/// Insert the lower 8-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRB.
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PINSRB,
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/// Insert the lower 16-bits of a 32-bit value to a vector,
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/// corresponds to X86::PINSRW.
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PINSRW, MMX_PINSRW,
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/// Shuffle 16 8-bit values within a vector.
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PSHUFB,
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/// Bitwise Logical AND NOT of Packed FP values.
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ANDNP,
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/// Copy integer sign.
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PSIGN,
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/// Blend where the selector is an immediate.
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BLENDI,
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/// Blend where the condition has been shrunk.
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/// This is used to emphasize that the condition mask is
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/// no more valid for generic VSELECT optimizations.
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SHRUNKBLEND,
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/// Combined add and sub on an FP vector.
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ADDSUB,
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// FP vector ops with rounding mode.
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FADD_RND,
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FSUB_RND,
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FMUL_RND,
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FDIV_RND,
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// Integer sub with unsigned saturation.
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SUBUS,
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/// Integer horizontal add.
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HADD,
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/// Integer horizontal sub.
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HSUB,
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/// Floating point horizontal add.
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FHADD,
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/// Floating point horizontal sub.
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FHSUB,
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/// Unsigned integer max and min.
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UMAX, UMIN,
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/// Signed integer max and min.
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SMAX, SMIN,
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/// Floating point max and min.
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FMAX, FMIN,
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/// Commutative FMIN and FMAX.
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FMAXC, FMINC,
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/// Floating point reciprocal-sqrt and reciprocal approximation.
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/// Note that these typically require refinement
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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// Thread Local Storage.
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TLSADDR,
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// Thread Local Storage. A call to get the start address
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// of the TLS block for the current module.
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TLSBASEADDR,
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// Thread Local Storage. When calling to an OS provided
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// thunk at the address from an earlier relocation.
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TLSCALL,
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// Exception Handling helpers.
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EH_RETURN,
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// SjLj exception handling setjmp.
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EH_SJLJ_SETJMP,
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// SjLj exception handling longjmp.
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EH_SJLJ_LONGJMP,
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/// Tail call return. See X86TargetLowering::LowerCall for
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/// the list of operands.
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TC_RETURN,
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// Vector move to low scalar and zero higher vector elements.
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VZEXT_MOVL,
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// Vector integer zero-extend.
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VZEXT,
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// Vector integer signed-extend.
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VSEXT,
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// Vector integer truncate.
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VTRUNC,
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// Vector integer truncate with mask.
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VTRUNCM,
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// Vector FP extend.
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VFPEXT,
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// Vector FP round.
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VFPROUND,
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// 128-bit vector logical left / right shift
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VSHLDQ, VSRLDQ,
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// Vector shift elements
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VSHL, VSRL, VSRA,
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// Vector shift elements by immediate
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VSHLI, VSRLI, VSRAI,
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// Vector packed double/float comparison.
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CMPP,
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// Vector integer comparisons.
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PCMPEQ, PCMPGT,
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// Vector integer comparisons, the result is in a mask vector.
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PCMPEQM, PCMPGTM,
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/// Vector comparison generating mask bits for fp and
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/// integer signed and unsigned data types.
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CMPM,
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CMPMU,
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// Arithmetic operations with FLAGS results.
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ADD, SUB, ADC, SBB, SMUL,
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INC, DEC, OR, XOR, AND,
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BEXTR, // Bit field extract
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UMUL, // LOW, HI, FLAGS = umul LHS, RHS
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// 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
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SMUL8, UMUL8,
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// 8-bit divrem that zero-extend the high result (AH).
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UDIVREM8_ZEXT_HREG,
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SDIVREM8_SEXT_HREG,
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// X86-specific multiply by immediate.
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MUL_IMM,
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// Vector bitwise comparisons.
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PTEST,
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// Vector packed fp sign bitwise comparisons.
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TESTP,
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// Vector "test" in AVX-512, the result is in a mask vector.
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TESTM,
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TESTNM,
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// OR/AND test for masks
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KORTEST,
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// Several flavors of instructions with vector shuffle behaviors.
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PACKSS,
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PACKUS,
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// Intra-lane alignr
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PALIGNR,
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// AVX512 inter-lane alignr
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VALIGN,
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PSHUFD,
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PSHUFHW,
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PSHUFLW,
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SHUFP,
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MOVDDUP,
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MOVSHDUP,
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MOVSLDUP,
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MOVLHPS,
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MOVLHPD,
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MOVHLPS,
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MOVLPS,
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MOVLPD,
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MOVSD,
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MOVSS,
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UNPCKL,
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UNPCKH,
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VPERMILPV,
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VPERMILPI,
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VPERMV,
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VPERMV3,
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VPERMIV3,
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VPERMI,
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VPERM2X128,
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VBROADCAST,
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// masked broadcast
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VBROADCASTM,
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// Insert/Extract vector element
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VINSERT,
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VEXTRACT,
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// Vector multiply packed unsigned doubleword integers
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PMULUDQ,
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// Vector multiply packed signed doubleword integers
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PMULDQ,
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// FMA nodes
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FMADD,
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FNMADD,
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FMSUB,
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FNMSUB,
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FMADDSUB,
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FMSUBADD,
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// FMA with rounding mode
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FMADD_RND,
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FNMADD_RND,
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FMSUB_RND,
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FNMSUB_RND,
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FMADDSUB_RND,
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FMSUBADD_RND,
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RNDSCALE,
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// Compress and expand
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COMPRESS,
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EXPAND,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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// Windows's _chkstk call to do stack probing.
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WIN_ALLOCA,
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// For allocating variable amounts of stack space when using
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// segmented stacks. Check if the current stacklet has enough space, and
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// falls back to heap allocation if not.
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SEG_ALLOCA,
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// Windows's _ftol2 runtime routine to do fptoui.
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WIN_FTOL,
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// Memory barrier
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MEMBARRIER,
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MFENCE,
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SFENCE,
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LFENCE,
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// Store FP status word into i16 register.
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FNSTSW16r,
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// Store contents of %ah into %eflags.
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SAHF,
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// Get a random integer and indicate whether it is valid in CF.
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RDRAND,
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// Get a NIST SP800-90B & C compliant random integer and
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// indicate whether it is valid in CF.
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RDSEED,
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PCMPISTRI,
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PCMPESTRI,
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// Test if in transactional execution.
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XTEST,
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// ERI instructions
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RSQRT28, RCP28, EXP2,
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// Compare and swap.
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LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LCMPXCHG8_DAG,
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LCMPXCHG16_DAG,
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// Load, scalar_to_vector, and zero extend.
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VZEXT_LOAD,
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// Store FP control world into i16 memory.
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FNSTCW16m,
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/// This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (int value
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/// and token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// This instruction implements SINT_TO_FP with the
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/// integer source in memory and FP reg result. This corresponds to the
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/// X86::FILD*m instructions. It has three inputs (token chain, address,
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/// and source type) and two outputs (FP value and token chain). FILD_FLAG
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/// also produces a flag).
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FILD,
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FILD_FLAG,
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/// This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// This instruction grabs the address of the next argument
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/// from a va_list. (reads and modifies the va_list in memory)
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VAARG_64
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// WARNING: Do not add anything in the end unless you want the node to
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// have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
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// thought as target memory ops!
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};
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}
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/// Define some predicates that are used for node matching.
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namespace X86 {
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/// Return true if the specified
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/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
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/// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
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bool isVEXTRACT128Index(SDNode *N);
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/// Return true if the specified
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/// INSERT_SUBVECTOR operand specifies a subvector insert that is
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/// suitable for input to VINSERTF128, VINSERTI128 instructions.
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bool isVINSERT128Index(SDNode *N);
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/// Return true if the specified
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/// EXTRACT_SUBVECTOR operand specifies a vector extract that is
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/// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
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bool isVEXTRACT256Index(SDNode *N);
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|
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/// Return true if the specified
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/// INSERT_SUBVECTOR operand specifies a subvector insert that is
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/// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
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bool isVINSERT256Index(SDNode *N);
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/// Return the appropriate
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/// immediate to extract the specified EXTRACT_SUBVECTOR index
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/// with VEXTRACTF128, VEXTRACTI128 instructions.
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unsigned getExtractVEXTRACT128Immediate(SDNode *N);
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/// Return the appropriate
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/// immediate to insert at the specified INSERT_SUBVECTOR index
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/// with VINSERTF128, VINSERT128 instructions.
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unsigned getInsertVINSERT128Immediate(SDNode *N);
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/// Return the appropriate
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/// immediate to extract the specified EXTRACT_SUBVECTOR index
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/// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
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unsigned getExtractVEXTRACT256Immediate(SDNode *N);
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/// Return the appropriate
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/// immediate to insert at the specified INSERT_SUBVECTOR index
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/// with VINSERTF64x4, VINSERTI64x4 instructions.
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unsigned getInsertVINSERT256Immediate(SDNode *N);
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/// Returns true if Elt is a constant zero or floating point constant +0.0.
|
|
bool isZeroNode(SDValue Elt);
|
|
|
|
/// Returns true of the given offset can be
|
|
/// fit into displacement field of the instruction.
|
|
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
|
|
bool hasSymbolicDisplacement = true);
|
|
|
|
|
|
/// Determines whether the callee is required to pop its
|
|
/// own arguments. Callee pop is necessary to support tail calls.
|
|
bool isCalleePop(CallingConv::ID CallingConv,
|
|
bool is64Bit, bool IsVarArg, bool TailCallOpt);
|
|
|
|
/// AVX512 static rounding constants. These need to match the values in
|
|
/// avx512fintrin.h.
|
|
enum STATIC_ROUNDING {
|
|
TO_NEAREST_INT = 0,
|
|
TO_NEG_INF = 1,
|
|
TO_POS_INF = 2,
|
|
TO_ZERO = 3,
|
|
CUR_DIRECTION = 4
|
|
};
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// X86 Implementation of the TargetLowering interface
|
|
class X86TargetLowering final : public TargetLowering {
|
|
public:
|
|
explicit X86TargetLowering(const X86TargetMachine &TM,
|
|
const X86Subtarget &STI);
|
|
|
|
unsigned getJumpTableEncoding() const override;
|
|
|
|
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
|
|
|
|
const MCExpr *
|
|
LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
|
|
const MachineBasicBlock *MBB, unsigned uid,
|
|
MCContext &Ctx) const override;
|
|
|
|
/// Returns relocation base for the given PIC jumptable.
|
|
SDValue getPICJumpTableRelocBase(SDValue Table,
|
|
SelectionDAG &DAG) const override;
|
|
const MCExpr *
|
|
getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
|
|
unsigned JTI, MCContext &Ctx) const override;
|
|
|
|
/// Return the desired alignment for ByVal aggregate
|
|
/// function arguments in the caller parameter area. For X86, aggregates
|
|
/// that contains are placed at 16-byte boundaries while the rest are at
|
|
/// 4-byte boundaries.
|
|
unsigned getByValTypeAlignment(Type *Ty) const override;
|
|
|
|
/// Returns the target specific optimal type for load
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
/// lowering. If DstAlign is zero that means it's safe to destination
|
|
/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
|
|
/// means there isn't a need to check it against alignment requirement,
|
|
/// probably because the source does not need to be loaded. If 'IsMemset' is
|
|
/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
|
|
/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
|
|
/// source is constant so it does not need to be loaded.
|
|
/// It returns EVT::Other if the type should be determined using generic
|
|
/// target-independent logic.
|
|
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
|
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
|
MachineFunction &MF) const override;
|
|
|
|
/// Returns true if it's safe to use load / store of the
|
|
/// specified type to expand memcpy / memset inline. This is mostly true
|
|
/// for all types except for some special cases. For example, on X86
|
|
/// targets without SSE2 f64 load / store are done with fldl / fstpl which
|
|
/// also does type conversion. Note the specified type doesn't have to be
|
|
/// legal as the hook is used before type legalization.
|
|
bool isSafeMemOpType(MVT VT) const override;
|
|
|
|
/// Returns true if the target allows
|
|
/// unaligned memory accesses. of the specified type. Returns whether it
|
|
/// is "fast" by reference in the second argument.
|
|
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
|
|
bool *Fast) const override;
|
|
|
|
/// Provide custom lowering hooks for some operations.
|
|
///
|
|
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
|
|
|
/// Replace the results of node with an illegal result
|
|
/// type with new values built out of custom code.
|
|
///
|
|
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
|
|
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
|
|
|
/// Return true if the target has native support for
|
|
/// the specified value type and it is 'desirable' to use the type for the
|
|
/// given node type. e.g. On x86 i16 is legal, but undesirable since i16
|
|
/// instruction encodings are longer and some i16 instructions are slow.
|
|
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
|
|
|
|
/// Return true if the target has native support for the
|
|
/// specified value type and it is 'desirable' to use the type. e.g. On x86
|
|
/// i16 is legal, but undesirable since i16 instruction encodings are longer
|
|
/// and some i16 instructions are slow.
|
|
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
|
|
|
|
MachineBasicBlock *
|
|
EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const override;
|
|
|
|
|
|
/// This method returns the name of a target specific DAG node.
|
|
const char *getTargetNodeName(unsigned Opcode) const override;
|
|
|
|
bool isCheapToSpeculateCttz() const override;
|
|
|
|
bool isCheapToSpeculateCtlz() const override;
|
|
|
|
/// Return the value type to use for ISD::SETCC.
|
|
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
|
|
|
|
/// Determine which of the bits specified in Mask are known to be either
|
|
/// zero or one and return them in the KnownZero/KnownOne bitsets.
|
|
void computeKnownBitsForTargetNode(const SDValue Op,
|
|
APInt &KnownZero,
|
|
APInt &KnownOne,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth = 0) const override;
|
|
|
|
/// Determine the number of bits in the operation that are sign bits.
|
|
unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
|
|
const SelectionDAG &DAG,
|
|
unsigned Depth) const override;
|
|
|
|
bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
|
|
int64_t &Offset) const override;
|
|
|
|
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
|
|
|
|
bool ExpandInlineAsm(CallInst *CI) const override;
|
|
|
|
ConstraintType
|
|
getConstraintType(const std::string &Constraint) const override;
|
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
|
/// The operand object must already have been set up with the operand type.
|
|
ConstraintWeight
|
|
getSingleConstraintMatchWeight(AsmOperandInfo &info,
|
|
const char *constraint) const override;
|
|
|
|
const char *LowerXConstraint(EVT ConstraintVT) const override;
|
|
|
|
/// Lower the specified operand into the Ops vector. If it is invalid, don't
|
|
/// add anything to Ops. If hasMemory is true it means one of the asm
|
|
/// constraint of the inline asm instruction being processed is 'm'.
|
|
void LowerAsmOperandForConstraint(SDValue Op,
|
|
std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const override;
|
|
|
|
unsigned getInlineAsmMemConstraint(
|
|
const std::string &ConstraintCode) const override {
|
|
// FIXME: Map different constraints differently.
|
|
return InlineAsm::Constraint_m;
|
|
}
|
|
|
|
/// Given a physical register constraint
|
|
/// (e.g. {edx}), return the register number and the register class for the
|
|
/// register. This should only be used for C_Register constraints. On
|
|
/// error, this returns a register number of 0.
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|
const std::string &Constraint,
|
|
MVT VT) const override;
|
|
|
|
/// Return true if the addressing mode represented
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
|
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
|
|
|
|
/// Return true if the specified immediate is legal
|
|
/// icmp immediate, that is the target has icmp instructions which can
|
|
/// compare a register against the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
bool isLegalICmpImmediate(int64_t Imm) const override;
|
|
|
|
/// Return true if the specified immediate is legal
|
|
/// add immediate, that is the target has add instructions which can
|
|
/// add a register and the immediate without having to materialize
|
|
/// the immediate into a register.
|
|
bool isLegalAddImmediate(int64_t Imm) const override;
|
|
|
|
/// \brief Return the cost of the scaling factor used in the addressing
|
|
/// mode represented by AM for this target, for a load/store
|
|
/// of the specified type.
|
|
/// If the AM is supported, the return value must be >= 0.
|
|
/// If the AM is not supported, it returns a negative value.
|
|
int getScalingFactorCost(const AddrMode &AM, Type *Ty) const override;
|
|
|
|
bool isVectorShiftByScalarCheap(Type *Ty) const override;
|
|
|
|
/// Return true if it's free to truncate a value of
|
|
/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
|
|
/// register EAX to i16 by referencing its sub-register AX.
|
|
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
|
|
bool isTruncateFree(EVT VT1, EVT VT2) const override;
|
|
|
|
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
|
|
|
|
/// Return true if any actual instruction that defines a
|
|
/// value of type Ty1 implicit zero-extends the value to Ty2 in the result
|
|
/// register. This does not necessarily include registers defined in
|
|
/// unknown ways, such as incoming arguments, or copies from unknown
|
|
/// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
|
|
/// does not necessarily apply to truncate instructions. e.g. on x86-64,
|
|
/// all instructions that define 32-bit values implicit zero-extend the
|
|
/// result out to 64 bits.
|
|
bool isZExtFree(Type *Ty1, Type *Ty2) const override;
|
|
bool isZExtFree(EVT VT1, EVT VT2) const override;
|
|
bool isZExtFree(SDValue Val, EVT VT2) const override;
|
|
|
|
/// Return true if folding a vector load into ExtVal (a sign, zero, or any
|
|
/// extend node) is profitable.
|
|
bool isVectorLoadExtDesirable(SDValue) const override;
|
|
|
|
/// Return true if an FMA operation is faster than a pair of fmul and fadd
|
|
/// instructions. fmuladd intrinsics will be expanded to FMAs when this
|
|
/// method returns true, otherwise fmuladd is expanded to fmul + fadd.
|
|
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
|
|
|
|
/// Return true if it's profitable to narrow
|
|
/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
|
|
/// from i32 to i8 but not from i32 to i16.
|
|
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
|
|
|
|
/// Returns true if the target can instruction select the
|
|
/// specified FP immediate natively. If false, the legalizer will
|
|
/// materialize the FP immediate as a load from a constant pool.
|
|
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
|
|
|
|
/// Targets can use this to indicate that they only support *some*
|
|
/// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
|
|
/// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
|
|
/// be legal.
|
|
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const override;
|
|
|
|
/// Similar to isShuffleMaskLegal. This is used by Targets can use this to
|
|
/// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
|
|
/// replace a VAND with a constant pool entry.
|
|
bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
|
|
EVT VT) const override;
|
|
|
|
/// If true, then instruction selection should
|
|
/// seek to shrink the FP constant of the specified type to a smaller type
|
|
/// in order to save space and / or reduce runtime.
|
|
bool ShouldShrinkFPConstant(EVT VT) const override {
|
|
// Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
|
|
// expensive than a straight movsd. On the other hand, it's important to
|
|
// shrink long double fp constant since fldt is very slow.
|
|
return !X86ScalarSSEf64 || VT == MVT::f80;
|
|
}
|
|
|
|
/// Return true if we believe it is correct and profitable to reduce the
|
|
/// load node to a smaller type.
|
|
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
|
|
EVT NewVT) const override;
|
|
|
|
/// Return true if the specified scalar FP type is computed in an SSE
|
|
/// register, not on the X87 floating point stack.
|
|
bool isScalarFPTypeInSSEReg(EVT VT) const {
|
|
return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
|
|
(VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
|
|
}
|
|
|
|
/// Return true if the target uses the MSVC _ftol2 routine for fptoui.
|
|
bool isTargetFTOL() const;
|
|
|
|
/// Return true if the MSVC _ftol2 routine should be used for fptoui to the
|
|
/// given type.
|
|
bool isIntegerTypeFTOL(EVT VT) const {
|
|
return isTargetFTOL() && VT == MVT::i64;
|
|
}
|
|
|
|
/// \brief Returns true if it is beneficial to convert a load of a constant
|
|
/// to just the constant itself.
|
|
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
|
Type *Ty) const override;
|
|
|
|
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
|
|
/// with this index.
|
|
bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
|
|
|
|
/// Intel processors have a unified instruction and data cache
|
|
const char * getClearCacheBuiltinName() const override {
|
|
return nullptr; // nothing to do, move along.
|
|
}
|
|
|
|
unsigned getRegisterByName(const char* RegName, EVT VT) const override;
|
|
|
|
/// This method returns a target specific FastISel object,
|
|
/// or null if the target does not support "fast" ISel.
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo) const override;
|
|
|
|
/// Return true if the target stores stack protector cookies at a fixed
|
|
/// offset in some non-standard address space, and populates the address
|
|
/// space and offset as appropriate.
|
|
bool getStackCookieLocation(unsigned &AddressSpace,
|
|
unsigned &Offset) const override;
|
|
|
|
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
|
|
SelectionDAG &DAG) const;
|
|
|
|
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
|
|
|
|
bool useLoadStackGuardNode() const override;
|
|
/// \brief Customize the preferred legalization strategy for certain types.
|
|
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
|
|
|
|
protected:
|
|
std::pair<const TargetRegisterClass *, uint8_t>
|
|
findRepresentativeClass(const TargetRegisterInfo *TRI,
|
|
MVT VT) const override;
|
|
|
|
private:
|
|
/// Keep a pointer to the X86Subtarget around so that we can
|
|
/// make the right decision when generating code for different targets.
|
|
const X86Subtarget *Subtarget;
|
|
const DataLayout *TD;
|
|
|
|
/// Select between SSE or x87 floating point ops.
|
|
/// When SSE is available, use it for f32 operations.
|
|
/// When SSE2 is available, use it for f64 operations.
|
|
bool X86ScalarSSEf32;
|
|
bool X86ScalarSSEf64;
|
|
|
|
/// A list of legal FP immediates.
|
|
std::vector<APFloat> LegalFPImmediates;
|
|
|
|
/// Indicate that this x86 target can instruction
|
|
/// select the specified FP immediate natively.
|
|
void addLegalFPImmediate(const APFloat& Imm) {
|
|
LegalFPImmediates.push_back(Imm);
|
|
}
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
SDValue LowerMemArgument(SDValue Chain,
|
|
CallingConv::ID CallConv,
|
|
const SmallVectorImpl<ISD::InputArg> &ArgInfo,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA, MachineFrameInfo *MFI,
|
|
unsigned i) const;
|
|
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
|
|
SDLoc dl, SelectionDAG &DAG,
|
|
const CCValAssign &VA,
|
|
ISD::ArgFlagsTy Flags) const;
|
|
|
|
// Call lowering helpers.
|
|
|
|
/// Check whether the call is eligible for tail call optimization. Targets
|
|
/// that want to do tail call optimization should implement this function.
|
|
bool IsEligibleForTailCallOptimization(SDValue Callee,
|
|
CallingConv::ID CalleeCC,
|
|
bool isVarArg,
|
|
bool isCalleeStructRet,
|
|
bool isCallerStructRet,
|
|
Type *RetTy,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
|
|
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
|
|
SDValue Chain, bool IsTailCall, bool Is64Bit,
|
|
int FPDiff, SDLoc dl) const;
|
|
|
|
unsigned GetAlignedArgumentStackSize(unsigned StackSize,
|
|
SelectionDAG &DAG) const;
|
|
|
|
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
|
|
bool isSigned,
|
|
bool isReplace) const;
|
|
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
|
|
int64_t Offset, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
|
|
SDLoc dl, SelectionDAG &DAG) const;
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
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SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const override;
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bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
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bool mayBeEmittedAsTailCall(CallInst *CI) const override;
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EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
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ISD::NodeType ExtendKind) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
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bool shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
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bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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TargetLoweringBase::AtomicRMWExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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LoadInst *
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lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
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bool needsCmpXchgNb(const Type *MemType) const;
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/// Utility function to emit atomic-load-arith operations (and, or, xor,
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/// nand, max, min, umax, umin). It takes the corresponding instruction to
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/// expand, the associated machine basic block, and the associated X86
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/// opcodes for reg/reg.
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MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Utility function to emit atomic-load-arith operations (and, or, xor,
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/// nand, add, sub, swap) for 64-bit operands on 32-bit target.
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MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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// Utility function to emit the low-level va_arg code for X86-64.
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|
MachineBasicBlock *EmitVAARG64WithCustomInserter(
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MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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/// Utility function to emit the xmm reg save portion of va_start.
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|
MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
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MachineInstr *BInstr,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
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|
MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
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|
MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
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|
MachineBasicBlock *BB) const;
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|
MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
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|
MachineBasicBlock *BB) const;
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|
MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
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|
MachineBasicBlock *BB) const;
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|
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|
MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const;
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|
|
|
MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const;
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|
|
|
MachineBasicBlock *emitFMA3Instr(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const;
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|
|
|
/// Emit nodes that will be selected as "test Op0,Op0", or something
|
|
/// equivalent, for use with the given x86 condition code.
|
|
SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl,
|
|
SelectionDAG &DAG) const;
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|
|
|
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
|
|
/// equivalent, for use with the given x86 condition code.
|
|
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl,
|
|
SelectionDAG &DAG) const;
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|
|
|
/// Convert a comparison if required by the subtarget.
|
|
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
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|
|
|
/// Use rsqrt* to speed up sqrt calculations.
|
|
SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
|
|
unsigned &RefinementSteps,
|
|
bool &UseOneConstNR) const override;
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|
|
|
/// Use rcp* to speed up fdiv calculations.
|
|
SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
|
|
unsigned &RefinementSteps) const override;
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|
|
|
/// Reassociate floating point divisions into multiply by reciprocal.
|
|
bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
|
|
};
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|
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|
namespace X86 {
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo);
|
|
}
|
|
}
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|
#endif // X86ISELLOWERING_H
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