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Fixes <rdar://problem/10235725> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
213 lines
7.6 KiB
C++
213 lines
7.6 KiB
C++
//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGInstrs class, which implements
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// scheduling for a MachineInstr-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SCHEDULEDAGINSTRS_H
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#define SCHEDULEDAGINSTRS_H
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include <map>
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namespace llvm {
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class MachineLoopInfo;
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class MachineDominatorTree;
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/// LoopDependencies - This class analyzes loop-oriented register
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/// dependencies, which are used to guide scheduling decisions.
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/// For example, loop induction variable increments should be
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/// scheduled as soon as possible after the variable's last use.
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///
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class LLVM_LIBRARY_VISIBILITY LoopDependencies {
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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public:
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typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
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LoopDeps;
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LoopDeps Deps;
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LoopDependencies(const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt) :
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MLI(mli), MDT(mdt) {}
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/// VisitLoop - Clear out any previous state and analyze the given loop.
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///
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void VisitLoop(const MachineLoop *Loop) {
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assert(Deps.empty() && "stale loop dependencies");
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MachineBasicBlock *Header = Loop->getHeader();
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SmallSet<unsigned, 8> LoopLiveIns;
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for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
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LE = Header->livein_end(); LI != LE; ++LI)
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LoopLiveIns.insert(*LI);
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const MachineDomTreeNode *Node = MDT.getNode(Header);
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const MachineBasicBlock *MBB = Node->getBlock();
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assert(Loop->contains(MBB) &&
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"Loop does not contain header!");
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VisitRegion(Node, MBB, Loop, LoopLiveIns);
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}
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private:
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void VisitRegion(const MachineDomTreeNode *Node,
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const MachineBasicBlock *MBB,
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const MachineLoop *Loop,
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const SmallSet<unsigned, 8> &LoopLiveIns) {
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unsigned Count = 0;
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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const MachineInstr *MI = I;
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if (MI->isDebugValue())
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continue;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned MOReg = MO.getReg();
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if (LoopLiveIns.count(MOReg))
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Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
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}
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++Count; // Not every iteration due to dbg_value above.
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}
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (std::vector<MachineDomTreeNode*>::const_iterator I =
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Children.begin(), E = Children.end(); I != E; ++I) {
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const MachineDomTreeNode *ChildNode = *I;
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MachineBasicBlock *ChildBlock = ChildNode->getBlock();
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if (Loop->contains(ChildBlock))
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VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
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}
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}
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};
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/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
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/// MachineInstrs.
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class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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const MachineFrameInfo *MFI;
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const InstrItineraryData *InstrItins;
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/// Defs, Uses - Remember where defs and uses of each physical register
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/// are as we iterate upward through the instructions. This is allocated
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/// here instead of inside BuildSchedGraph to avoid the need for it to be
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/// initialized and destructed for each block.
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std::vector<std::vector<SUnit *> > Defs;
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std::vector<std::vector<SUnit *> > Uses;
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/// PendingLoads - Remember where unknown loads are after the most recent
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/// unknown store, as we iterate. As with Defs and Uses, this is here
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/// to minimize construction/destruction.
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std::vector<SUnit *> PendingLoads;
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/// LoopRegs - Track which registers are used for loop-carried dependencies.
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///
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LoopDependencies LoopRegs;
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/// LoopLiveInRegs - Track which regs are live into a loop, to help guide
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/// back-edge-aware scheduling.
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///
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SmallSet<unsigned, 8> LoopLiveInRegs;
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protected:
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/// DbgValues - Remember instruction that preceeds DBG_VALUE.
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typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
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DbgValueVector;
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DbgValueVector DbgValues;
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MachineInstr *FirstDbgValue;
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public:
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MachineBasicBlock::iterator Begin; // The beginning of the range to
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// be scheduled. The range extends
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// to InsertPos.
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unsigned InsertPosIndex; // The index in BB of InsertPos.
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explicit ScheduleDAGInstrs(MachineFunction &mf,
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const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt);
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virtual ~ScheduleDAGInstrs() {}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(MachineInstr *MI) {
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#ifndef NDEBUG
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const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
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#endif
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SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
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assert((Addr == 0 || Addr == &SUnits[0]) &&
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"SUnits std::vector reallocated on the fly!");
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// Run - perform scheduling.
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///
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void Run(MachineBasicBlock *bb,
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MachineBasicBlock::iterator begin,
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MachineBasicBlock::iterator end,
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unsigned endindex);
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/// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
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/// input.
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virtual void BuildSchedGraph(AliasAnalysis *AA);
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/// AddSchedBarrierDeps - Add dependencies from instructions in the current
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/// list of instructions being scheduled to scheduling barrier. We want to
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/// make sure instructions which define registers that are either used by
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/// the terminator or are live-out are properly scheduled. This is
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/// especially important when the definition latency of the return value(s)
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/// are too high to be hidden by the branch or when the liveout registers
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/// used by instructions in the fallthrough block.
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void AddSchedBarrierDeps();
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/// ComputeLatency - Compute node latency.
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///
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virtual void ComputeLatency(SUnit *SU);
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/// ComputeOperandLatency - Override dependence edge latency using
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/// operand use/def information
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///
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virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
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SDep& dep) const;
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virtual MachineBasicBlock *EmitSchedule();
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/// StartBlock - Prepare to perform scheduling in the given block.
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///
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virtual void StartBlock(MachineBasicBlock *BB);
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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/// FinishBlock - Clean up after scheduling in the given block.
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///
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virtual void FinishBlock();
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virtual void dumpNode(const SUnit *SU) const;
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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};
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}
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#endif
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