Tom Stellard 04c559569f R600: Simplify handling of private address space ... The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-22 18:19:10 +00:00
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AArch64	[AArch64] Add the constraint to NEON scalar mla/mls instructions.	2013-10-21 20:11:47 +00:00
ARM	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
CPP	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Generic	Change objectsize intrinsic to accept different address spaces.	2013-10-07 18:06:48 +00:00
Hexagon	TBAA: remove !tbaa from testing cases when they are not needed.	2013-09-30 18:17:35 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	[mips][msa] Fix definition of SLD instruction.	2013-10-21 11:47:56 +00:00
MSP430	Fix MSP430 calling convention to match MSPGCC	2013-10-15 08:19:39 +00:00
NVPTX	[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc	2013-10-11 12:39:39 +00:00
PowerPC	Update PPC loop tests after SCEV non-unit-stride checkin r193015.	2013-10-19 00:14:04 +00:00
R600	R600: Simplify handling of private address space	2013-10-22 18:19:10 +00:00
SPARC	[Sparc] Disable tail call optimization for sparc64.	2013-10-09 12:50:39 +00:00
SystemZ	Replace sra with srl if a single sign bit is required	2013-10-17 11:16:57 +00:00
Thumb	17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets	2013-10-17 19:52:05 +00:00
Thumb2	MachineSink: Fix and tweak critical-edge breaking heuristic.	2013-10-14 16:57:17 +00:00
X86	AVX-512: aligned / unaligned load and store for 512-bit integer vectors.	2013-10-22 09:19:28 +00:00
XCore	XCore target fix bug in emitArrayBound() causing segmentation fault	2013-10-11 10:27:13 +00:00