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f90a656a9f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16526 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.7 KiB
TableGen
45 lines
1.7 KiB
TableGen
//===- SparcV8RegisterInfo.td - SparcV8 Register defs ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the SparcV8 register file
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//===----------------------------------------------------------------------===//
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class SparcReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "V8";
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}
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include "../SparcRegisterInfo.td"
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// Register classes.
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//
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5,
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G1, G2, G3, G4, G5, G6, G7,
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O0, O1, O2, O3, O4, O5, O7,
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// Non-allocatable regs
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O6, I6, I7, G0]> {
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let Methods = [{
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iterator allocation_order_end(MachineFunction &MF) const {
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return end()-4; // Don't allocate special registers
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}
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}];
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}
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def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
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F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
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F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
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def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7,
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D8, D9, D10, D11, D12, D13, D14, D15]>;
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