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https://github.com/c64scene-ar/llvm-6502.git
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283b399377
behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
325 lines
13 KiB
C++
325 lines
13 KiB
C++
//===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "systemz-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class SystemZDisassembler : public MCDisassembler {
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public:
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SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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virtual ~SystemZDisassembler() {}
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// Override MCDisassembler.
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DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
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const MemoryObject ®ion, uint64_t address,
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raw_ostream &vStream,
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raw_ostream &cStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createSystemZDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new SystemZDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeSystemZDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheSystemZTarget,
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createSystemZDisassembler);
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}
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static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
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const unsigned *Regs) {
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assert(RegNo < 16 && "Invalid register");
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RegNo = Regs[RegNo];
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if (RegNo == 0)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::CreateReg(RegNo));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs);
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}
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static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs);
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}
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static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
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}
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static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs);
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}
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static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs);
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}
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static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs);
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}
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static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs);
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}
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static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs);
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}
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template<unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::CreateImm(Imm));
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return MCDisassembler::Success;
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}
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template<unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder) {
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return decodeUImmOperand<4>(Inst, Imm);
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}
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static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeUImmOperand<4>(Inst, Imm);
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}
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static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeUImmOperand<6>(Inst, Imm);
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}
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static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeUImmOperand<8>(Inst, Imm);
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}
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static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeUImmOperand<16>(Inst, Imm);
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}
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static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeUImmOperand<32>(Inst, Imm);
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}
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static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeSImmOperand<8>(Inst, Imm);
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}
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static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeSImmOperand<16>(Inst, Imm);
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}
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static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, const void *Decoder) {
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return decodeSImmOperand<32>(Inst, Imm);
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}
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template<unsigned N>
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static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address) {
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assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
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Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodePC16DBLOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder) {
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return decodePCDBLOperand<16>(Inst, Imm, Address);
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}
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static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const void *Decoder) {
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return decodePCDBLOperand<32>(Inst, Imm, Address);
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}
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static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Base = Field >> 12;
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uint64_t Disp = Field & 0xfff;
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assert(Base < 16 && "Invalid BDAddr12");
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Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::CreateImm(Disp));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Base = Field >> 20;
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uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
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assert(Base < 16 && "Invalid BDAddr20");
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Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Index = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Index < 16 && "Invalid BDXAddr12");
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Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::CreateImm(Disp));
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Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Index = Field >> 24;
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uint64_t Base = (Field >> 20) & 0xf;
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uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
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assert(Index < 16 && "Invalid BDXAddr20");
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Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
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Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Length = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Length < 256 && "Invalid BDLAddr12Len8");
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Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::CreateImm(Disp));
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Inst.addOperand(MCOperand::CreateImm(Length + 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
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}
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static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
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}
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static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst,
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uint64_t Field,
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uint64_t Address,
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const void *Decoder) {
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return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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#include "SystemZGenDisassemblerTables.inc"
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DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,
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raw_ostream &os,
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raw_ostream &cs) const {
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// Get the first two bytes of the instruction.
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uint8_t Bytes[6];
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Size = 0;
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if (Region.readBytes(Address, 2, Bytes) == -1)
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return MCDisassembler::Fail;
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// The top 2 bits of the first byte specify the size.
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const uint8_t *Table;
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if (Bytes[0] < 0x40) {
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Size = 2;
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Table = DecoderTable16;
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} else if (Bytes[0] < 0xc0) {
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Size = 4;
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Table = DecoderTable32;
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} else {
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Size = 6;
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Table = DecoderTable48;
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}
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// Read any remaining bytes.
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if (Size > 2 && Region.readBytes(Address + 2, Size - 2, Bytes + 2) == -1)
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return MCDisassembler::Fail;
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// Construct the instruction.
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uint64_t Inst = 0;
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for (uint64_t I = 0; I < Size; ++I)
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Inst = (Inst << 8) | Bytes[I];
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return decodeInstruction(Table, MI, Inst, Address, this, STI);
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}
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