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subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
3.0 KiB
C++
85 lines
3.0 KiB
C++
//==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subtarget options of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCSUBTARGET_H
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#define LLVM_MC_MCSUBTARGET_H
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include <string>
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namespace llvm {
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class StringRef;
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//===----------------------------------------------------------------------===//
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///
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/// MCSubtargetInfo - Generic base class for all target subtargets.
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///
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class MCSubtargetInfo {
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std::string TargetTriple; // Target triple
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const SubtargetFeatureKV *ProcFeatures; // Processor feature list
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const SubtargetFeatureKV *ProcDesc; // Processor descriptions
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const SubtargetInfoKV *ProcSchedModel; // Scheduler machine model
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const InstrStage *Stages; // Instruction itinerary stages
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const unsigned *OperandCycles; // Itinerary operand cycles
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const unsigned *ForwardingPaths; // Forwarding paths
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unsigned NumFeatures; // Number of processor features
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unsigned NumProcs; // Number of processors
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uint64_t FeatureBits; // Feature bits for current CPU + FS
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public:
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void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
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const SubtargetFeatureKV *PF,
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const SubtargetFeatureKV *PD,
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const SubtargetInfoKV *ProcSched,
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const InstrStage *IS,
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const unsigned *OC, const unsigned *FP,
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unsigned NF, unsigned NP);
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/// getTargetTriple - Return the target triple string.
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StringRef getTargetTriple() const {
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return TargetTriple;
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}
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/// getFeatureBits - Return the feature bits.
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///
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uint64_t getFeatureBits() const {
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return FeatureBits;
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}
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/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
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/// feature string), recompute and return feature bits.
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uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version does not change the implied bits.
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uint64_t ToggleFeature(uint64_t FB);
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/// ToggleFeature - Toggle a feature and returns the re-computed feature
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/// bits. This version will also change all implied bits.
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uint64_t ToggleFeature(StringRef FS);
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/// getSchedModelForCPU - Get the machine model of a CPU.
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///
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MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
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/// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
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///
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InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
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};
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} // End llvm namespace
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#endif
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