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SingleSource except oopack and Oscar. (Sorry, Oscar.) include/llvm/Target/TargetInstrInfo.h: Remove virtual print method. Add accessors for ImplicitUses/Defs. lib/Target/TargetInstrInfo.cpp: Remove virtual print method. If you really wanted this, just use MI->print(O, TM); instead... lib/Target/X86: FloatingPoint.cpp: ...like this. X86InstrInfo.h: Remove virtual print method. Define the PrintImplUses target-specific flag bit. X86InstrInfo.def: Add the PrintImplUses flag to all the instructions which implicitly use CL, because the assembler needs to see the CL in order to generate the right instruction. Printer.cpp: Ditch fnIndex at Chris's request. Now we use CurrentFnName to name constants in the constant pool for each function instead. This avoids keeping state between runOnMachineFunction() invocations, which is a no-no. Having MangledGlobals be global is a bogon I'd like to get rid of too, but making it a static member of Printer causes link errors (why???). Make NumberForBB into a member of Printer instead of a global, too. Make printOp and printMemReference into methods of Printer. X86InstrInfo::print is now Printer::printMachineInstruction, because TargetInstrInfo::print is history. (Because of this, we have to qualify the names of some TargetInstrInfo methods we call.) Print out the ImplicitUses field of any instruction we print that has the PrintImplUses bit set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6924 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
6.4 KiB
C++
174 lines
6.4 KiB
C++
//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "X86RegisterInfo.h"
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace X86II {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction types. These are the standard/most common forms for X86
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// instructions.
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//
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// Raw - This form is for instructions that don't have any operands, so
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/// they are just a fixed opcode value, like 'leave'.
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RawFrm = 1,
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/// AddRegFrm - This form is used for instructions like 'push r32' that have
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/// their one register operand added to their opcode.
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AddRegFrm = 2,
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/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is a register.
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///
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MRMDestReg = 3,
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/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is memory.
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///
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MRMDestMem = 4,
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/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is a register.
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///
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MRMSrcReg = 5,
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/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is memory.
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///
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MRMSrcMem = 6,
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/// MRMS[0-7][rm] - These forms are used to represent instructions that use
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/// a Mod/RM byte, and use the middle field to hold extended opcode
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/// information. In the intel manual these are represented as /0, /1, ...
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///
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// First, instructions that operate on a register r/m operand...
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MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3
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MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7
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// Next, instructions that operate on a memory r/m operand...
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MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3
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MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7
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FormMask = 31,
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//===------------------------------------------------------------------===//
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// Actual flags...
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/// Void - Set if this instruction produces no value
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Void = 1 << 5,
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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OpSize = 1 << 6,
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to
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// obtain the setting of this field. If no bits in this field is set, there
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// is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Mask = 0xF << 7,
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Op0Shift = 7,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << 7,
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 2 << 7, D9 = 3 << 7, DA = 4 << 7, DB = 5 << 7,
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DC = 6 << 7, DD = 7 << 7, DE = 8 << 7, DF = 9 << 7,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of a memory operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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Arg8 = 1 << 11,
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Arg16 = 2 << 11,
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Arg32 = 3 << 11,
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Arg64 = 4 << 11, // 64 bit int argument for FILD64
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ArgF32 = 5 << 11,
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ArgF64 = 6 << 11,
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ArgF80 = 7 << 11,
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ArgMask = 7 << 11,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << 14,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << 14,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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//
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OneArgFPRW = 3 << 14,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << 14,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 5 << 14,
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// FPTypeMask - Mask for all of the FP types...
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FPTypeMask = 7 << 14,
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// PrintImplUses - Print out implicit uses in the assembly output.
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PrintImplUses = 1 << 17
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// Bits 18 -> 31 are unused
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};
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}
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class X86InstrInfo : public TargetInstrInfo {
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const X86RegisterInfo RI;
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public:
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X86InstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
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///
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MachineInstr* createNOPinstr() const;
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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bool isNOPinstr(const MachineInstr &MI) const;
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified opcode number.
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//
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unsigned char getBaseOpcodeFor(unsigned Opcode) const;
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};
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#endif
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