mirror of
https://github.com/c64scene-ar/llvm-6502.git
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053c1da8d9
only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46483 91177308-0d34-0410-b5e6-96231b3b80d8
313 lines
9.1 KiB
TableGen
313 lines
9.1 KiB
TableGen
//==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Cell SPU instruction formats. Note that these are notationally similar to
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// PowerPC, like "A-Form". But the sizes of operands and fields differ.
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// This was kiped from the PPC instruction formats (seemed like a good idea...)
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class I<dag OOL, dag IOL, string asmstr, InstrItinClass itin>
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: Instruction {
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field bits<32> Inst;
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let Namespace = "SPU";
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let OutOperandList = OOL;
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let InOperandList = IOL;
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let AsmString = asmstr;
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let Itinerary = itin;
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}
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// RR Format
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class RRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin> {
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bits<7> RA;
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bits<7> RB;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-10} = opcode;
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let Inst{11-17} = RB;
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let Inst{18-24} = RA;
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let Inst{25-31} = RT;
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}
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let RB = 0 in {
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// RR Format, where RB is zeroed (dont care):
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class RRForm_1<bits<11> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
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{ }
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let RA = 0 in {
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// RR Format, where RA and RB are zeroed (dont care):
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// Used for reads from status control registers (see FPSCRRr32)
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class RRForm_2<bits<11> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
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{ }
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}
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}
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let RT = 0 in {
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// RR Format, where RT is zeroed (don't care), or as the instruction handbook
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// says, "RT is a false target." Used in "Halt if" instructions
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class RRForm_3<bits<11> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
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{ }
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}
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// RRR Format
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class RRRForm<bits<4> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<7> RA;
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bits<7> RB;
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bits<7> RC;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-3} = opcode;
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let Inst{4-10} = RT;
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let Inst{11-17} = RB;
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let Inst{18-24} = RA;
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let Inst{25-31} = RC;
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}
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// RI7 Format
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class RI7Form<bits<11> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<7> i7;
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bits<7> RA;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-10} = opcode;
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let Inst{11-17} = i7;
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let Inst{18-24} = RA;
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let Inst{25-31} = RT;
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}
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// CVTIntFp Format
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class CVTIntFPForm<bits<10> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<7> RA;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-9} = opcode;
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let Inst{10-17} = 0;
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let Inst{18-24} = RA;
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let Inst{25-31} = RT;
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}
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let RA = 0 in {
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class BICondForm<bits<11> opcode, string asmstr, list<dag> pattern>
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: RRForm<opcode, (outs), (ins R32C:$rA, R32C:$func), asmstr,
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BranchResolv, pattern>
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{ }
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let RT = 0 in {
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// Branch instruction format (without D/E flag settings)
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class BRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
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{ }
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class BIForm<bits<11> opcode, string asmstr, list<dag> pattern>
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: RRForm<opcode, (outs), (ins R32C:$func), asmstr, BranchResolv,
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pattern>
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{ }
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let RB = 0 in {
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// Return instruction (bi, branch indirect), RA is zero (LR):
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class RETForm<string asmstr, list<dag> pattern>
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: BRForm<0b00010101100, (outs), (ins), asmstr, BranchResolv,
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pattern>
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{ }
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}
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}
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}
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// Branch indirect external data forms:
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class BISLEDForm<bits<2> DE_flag, string asmstr, list<dag> pattern>
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: I<(outs), (ins indcalltarget:$func), asmstr, BranchResolv>
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{
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bits<7> Rcalldest;
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let Pattern = pattern;
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let Inst{0-10} = 0b11010101100;
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let Inst{11} = 0;
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let Inst{12-13} = DE_flag;
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let Inst{14-17} = 0b0000;
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let Inst{18-24} = Rcalldest;
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let Inst{25-31} = 0b0000000;
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}
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// RI10 Format
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class RI10Form<bits<8> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<10> i10;
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bits<7> RA;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-7} = opcode;
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let Inst{8-17} = i10;
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let Inst{18-24} = RA;
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let Inst{25-31} = RT;
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}
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// RI10 Format, where the constant is zero (or effectively ignored by the
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// SPU)
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class RI10Form_1<bits<8> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<7> RA;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-7} = opcode;
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let Inst{8-17} = 0;
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let Inst{18-24} = RA;
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let Inst{25-31} = RT;
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}
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// RI10 Format, where RT is ignored.
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// This format is used primarily by the Halt If ... Immediate set of
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// instructions
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class RI10Form_2<bits<8> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<10> i10;
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bits<7> RA;
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let Pattern = pattern;
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let Inst{0-7} = opcode;
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let Inst{8-17} = i10;
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let Inst{18-24} = RA;
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let Inst{25-31} = 0;
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}
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// RI16 Format
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class RI16Form<bits<9> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<16> i16;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-8} = opcode;
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let Inst{9-24} = i16;
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let Inst{25-31} = RT;
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}
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// Specialized version of the RI16 Format for unconditional branch relative and
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// branch absolute, branch and set link. Note that for branch and set link, the
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// link register doesn't have to be $lr, but this is actually hard coded into
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// the instruction pattern.
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let RT = 0 in {
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class UncondBranch<bits<9> opcode, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
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{ }
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class BranchSetLink<bits<9> opcode, dag OOL, dag IOL, string asmstr,
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list<dag> pattern>
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: RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
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{ }
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}
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//===----------------------------------------------------------------------===//
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// Specialized versions of RI16:
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//===----------------------------------------------------------------------===//
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// RI18 Format
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class RI18Form<bits<7> opcode, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<OOL, IOL, asmstr, itin>
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{
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bits<18> i18;
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bits<7> RT;
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let Pattern = pattern;
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let Inst{0-6} = opcode;
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let Inst{7-24} = i18;
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let Inst{25-31} = RT;
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}
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//===----------------------------------------------------------------------===//
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// Instruction formats for intrinsics:
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//===----------------------------------------------------------------------===//
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// RI10 Format for v8i16 intrinsics
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class RI10_Int_v8i16<bits<8> opcode, string opc, InstrItinClass itin,
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Intrinsic IntID> :
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RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
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!strconcat(opc, " $rT, $rA, $val"), itin,
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[(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
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i16ImmSExt10:$val))] >;
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class RI10_Int_v4i32<bits<8> opcode, string opc, InstrItinClass itin,
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Intrinsic IntID> :
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RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
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!strconcat(opc, " $rT, $rA, $val"), itin,
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[(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
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i32ImmSExt10:$val))] >;
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// RR Format for v8i16 intrinsics
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class RR_Int_v8i16<bits<11> opcode, string opc, InstrItinClass itin,
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Intrinsic IntID> :
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RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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!strconcat(opc, " $rT, $rA, $rB"), itin,
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[(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
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(v8i16 VECREG:$rB)))] >;
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// RR Format for v4i32 intrinsics
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class RR_Int_v4i32<bits<11> opcode, string opc, InstrItinClass itin,
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Intrinsic IntID> :
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RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
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!strconcat(opc, " $rT, $rA, $rB"), itin,
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[(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
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(v4i32 VECREG:$rB)))] >;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions, like call frames:
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//===----------------------------------------------------------------------===//
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class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
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: I<OOL, IOL, asmstr, NoItinerary> {
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let Pattern = pattern;
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let Inst{31-0} = 0;
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}
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