mirror of
https://github.com/c64scene-ar/llvm-6502.git
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053c1da8d9
only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46483 91177308-0d34-0410-b5e6-96231b3b80d8
155 lines
4.5 KiB
LLVM
155 lines
4.5 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
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; RUN: grep il %t1.s | count 16
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; RUN: grep ilhu %t1.s | count 8
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; RUN: grep ilh %t1.s | count 13
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; RUN: grep iohl %t1.s | count 7
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; RUN: grep lqa %t1.s | count 6
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; RUN: grep 24672 %t1.s | count 2
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; RUN: grep 16429 %t1.s | count 1
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; RUN: grep 63572 %t1.s | count 1
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; RUN: grep 4660 %t1.s | count 1
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; RUN: grep 22136 %t1.s | count 1
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; RUN: grep 43981 %t1.s | count 1
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; RUN: grep 61202 %t1.s | count 1
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; RUN: grep 16393 %t1.s | count 1
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; RUN: grep 8699 %t1.s | count 1
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; RUN: grep 21572 %t1.s | count 1
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; RUN: grep 11544 %t1.s | count 1
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; RUN: grep 1311768467750121234 %t1.s | count 1
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; RUN: grep lqd %t2.s | count 6
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
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target triple = "spu-unknown-elf"
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; Vector constant load tests:
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; IL <reg>, 2
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define <4 x i32> @v4i32_constvec() {
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ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 >
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}
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; Spill to constant pool
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define <4 x i32> @v4i32_constpool() {
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ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 >
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}
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; Max negative range for IL
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define <4 x i32> @v4i32_constvec_2() {
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ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 >
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}
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; ILHU <reg>, 73 (0x49)
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; 4784128 = 0x490000
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define <4 x i32> @v4i32_constvec_3() {
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ret <4 x i32> < i32 4784128, i32 4784128,
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i32 4784128, i32 4784128 >
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}
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; ILHU <reg>, 61 (0x3d)
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; IOHL <reg>, 15395 (0x3c23)
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define <4 x i32> @v4i32_constvec_4() {
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ret <4 x i32> < i32 4013091, i32 4013091,
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i32 4013091, i32 4013091 >
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}
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; ILHU <reg>, 0x5050 (20560)
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; IOHL <reg>, 0x5050 (20560)
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; Tests for whether we expand the size of the bit pattern properly, because
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; this could be interpreted as an i8 pattern (0x50)
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define <4 x i32> @v4i32_constvec_5() {
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ret <4 x i32> < i32 1347440720, i32 1347440720,
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i32 1347440720, i32 1347440720 >
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}
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; ILH
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define <8 x i16> @v8i16_constvec_1() {
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ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767,
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i16 32767, i16 32767, i16 32767, i16 32767 >
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}
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; ILH
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define <8 x i16> @v8i16_constvec_2() {
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ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511,
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i16 511, i16 511, i16 511 >
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}
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; ILH
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define <8 x i16> @v8i16_constvec_3() {
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ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512,
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i16 -512, i16 -512, i16 -512 >
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}
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; ILH <reg>, 24672 (0x6060)
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; Tests whether we expand the size of the bit pattern properly, because
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; this could be interpreted as an i8 pattern (0x60)
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define <8 x i16> @v8i16_constvec_4() {
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ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672,
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i16 24672, i16 24672, i16 24672 >
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}
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; ILH <reg>, 24672 (0x6060)
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; Tests whether we expand the size of the bit pattern properly, because
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; this is an i8 pattern but has to be expanded out to i16 to load it
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; properly into the vector register.
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define <16 x i8> @v16i8_constvec_1() {
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ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96,
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i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96 >
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}
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define <4 x float> @v4f32_constvec_1() {
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entry:
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ret <4 x float> < float 0x4005BF0A80000000,
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float 0x4005BF0A80000000,
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float 0x4005BF0A80000000,
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float 0x4005BF0A80000000 >
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}
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define <4 x float> @v4f32_constvec_2() {
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entry:
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ret <4 x float> < float 0.000000e+00,
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float 0.000000e+00,
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float 0.000000e+00,
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float 0.000000e+00 >
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}
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define <4 x float> @v4f32_constvec_3() {
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entry:
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ret <4 x float> < float 0x4005BF0A80000000,
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float 0x3810000000000000,
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float 0x47EFFFFFE0000000,
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float 0x400921FB60000000 >
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}
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; 1311768467750121234 => 0x 12345678 abcdef12
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; HI32_hi: 4660
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; HI32_lo: 22136
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; LO32_hi: 43981
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; LO32_lo: 61202
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define <2 x i64> @i64_constvec_1() {
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entry:
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ret <2 x i64> < i64 1311768467750121234,
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i64 1311768467750121234 >
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}
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define <2 x i64> @i64_constvec_2() {
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entry:
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ret <2 x i64> < i64 1, i64 1311768467750121234 >
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}
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define <2 x double> @f64_constvec_1() {
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entry:
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ret <2 x double> < double 0x400921fb54442d18,
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double 0xbff6a09e667f3bcd >
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}
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; 0x400921fb 54442d18 ->
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; (ILHU 0x4009 [16393]/IOHL 0x21fb [ 8699])
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; (ILHU 0x5444 [21572]/IOHL 0x2d18 [11544])
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define <2 x double> @f64_constvec_2() {
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entry:
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ret <2 x double> < double 0x400921fb54442d18,
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double 0x400921fb54442d18 >
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}
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