Matt Arsenault 054f4eccd2 R600: Fix trunc store from i64 to i1 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-12 18:45:52 +00:00
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AArch64
ARM	ARM: correct Dwarf output for non-contiguous VFP saves.	2014-03-12 11:29:23 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.	2014-03-12 11:54:00 +00:00
MSP430
NVPTX
PowerPC
R600	R600: Fix trunc store from i64 to i1	2014-03-12 18:45:52 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)	2014-03-11 15:49:24 +00:00
XCore