Vasileios Kalintiris 0563ea452c [mips] Avoid redundant sign extension of the result of binary bitwise instructions. ... Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7581 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229675 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-18 14:57:05 +00:00
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AArch64	AArch64: Safely handle the incoming sret call argument.	2015-02-16 18:10:47 +00:00
ARM	[ARM] Add missing M/R class CPUs	2015-02-18 10:33:30 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips] Avoid redundant sign extension of the result of binary bitwise instructions.	2015-02-18 14:57:05 +00:00
MSP430
NVPTX
PowerPC	Move ABI handling and 64-bitness to the PowerPC target machine.	2015-02-17 06:45:15 +00:00
R600	R600/SI: Add missing offset operand to buffer bothen	2015-02-18 02:04:38 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86	Fixes two issue in SimplifyDemandedBits of sext_in_reg:	2015-02-18 09:43:40 +00:00
XCore