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d43b5c97cf
This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.7 KiB
TableGen
42 lines
1.7 KiB
TableGen
//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent scheduling interfaces which should
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// be implemented by each target which is using TableGen based scheduling.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/TargetItinerary.td"
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// The SchedMachineModel is defined by subtargets for three categories of data:
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// 1) Basic properties for coarse grained instruction cost model.
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// 2) Scheduler Read/Write resources for simple per-opcode cost model.
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// 3) Instruction itineraties for detailed reservation tables.
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//
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// Default values for basic properties are defined in MCSchedModel. "-1"
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// indicates that the property is not overriden by the target description.
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class SchedMachineModel {
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int IssueWidth = -1; // Max instructions that may be scheduled per cycle.
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int MinLatency = -1; // Determines which instrucions are allowed in a group.
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// (-1) inorder (0) ooo, (1): inorder +var latencies.
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int LoadLatency = -1; // Cycles for loads to access the cache.
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int HighLatency = -1; // Approximation of cycles for "high latency" ops.
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int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
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ProcessorItineraries Itineraries = NoItineraries;
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bit NoModel = 0; // Special tag to indicate missing machine model.
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}
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def NoSchedModel : SchedMachineModel {
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let NoModel = 1;
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}
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// TODO: Define classes for processor and scheduler resources.
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