mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f0569be4a9
DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
145 lines
4.8 KiB
LLVM
145 lines
4.8 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
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; RUN: grep lqa %t1.s | count 5
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; RUN: grep lqd %t1.s | count 11
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; RUN: grep rotqbyi %t1.s | count 7
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; RUN: grep xshw %t1.s | count 1
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; RUN: grep andi %t1.s | count 5
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; RUN: grep cbd %t1.s | count 3
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; RUN: grep chd %t1.s | count 1
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; RUN: grep cwd %t1.s | count 3
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; RUN: grep shufb %t1.s | count 7
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; RUN: grep stqd %t1.s | count 7
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; RUN: grep iohl %t2.s | count 16
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; RUN: grep ilhu %t2.s | count 16
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; RUN: grep lqd %t2.s | count 16
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; RUN: grep rotqbyi %t2.s | count 7
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; RUN: grep xshw %t2.s | count 1
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; RUN: grep andi %t2.s | count 5
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; RUN: grep cbd %t2.s | count 3
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; RUN: grep chd %t2.s | count 1
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; RUN: grep cwd %t2.s | count 3
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; RUN: grep shufb %t2.s | count 7
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; RUN: grep stqd %t2.s | count 7
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; ModuleID = 'struct_1.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; struct hackstate {
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; unsigned char c1; // offset 0 (rotate left by 13 bytes to byte 3)
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; unsigned char c2; // offset 1 (rotate left by 14 bytes to byte 3)
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; unsigned char c3; // offset 2 (rotate left by 15 bytes to byte 3)
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; int i1; // offset 4 (rotate left by 4 bytes to byte 0)
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; short s1; // offset 8 (rotate left by 6 bytes to byte 2)
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; int i2; // offset 12 [ignored]
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; unsigned char c4; // offset 16 [ignored]
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; unsigned char c5; // offset 17 [ignored]
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; unsigned char c6; // offset 18 (rotate left by 14 bytes to byte 3)
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; unsigned char c7; // offset 19 (no rotate, in preferred slot)
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; int i3; // offset 20 [ignored]
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; int i4; // offset 24 [ignored]
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; int i5; // offset 28 [ignored]
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; int i6; // offset 32 (no rotate, in preferred slot)
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; }
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%struct.hackstate = type { i8, i8, i8, i32, i16, i32, i8, i8, i8, i8, i32, i32, i32, i32 }
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; struct hackstate state = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
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@state = global %struct.hackstate zeroinitializer, align 16
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define i8 @get_hackstate_c1() zeroext nounwind {
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entry:
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%tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16
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ret i8 %tmp2
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}
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define i8 @get_hackstate_c2() zeroext nounwind {
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entry:
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%tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16
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ret i8 %tmp2
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}
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define i8 @get_hackstate_c3() zeroext nounwind {
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entry:
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%tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16
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ret i8 %tmp2
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}
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define i32 @get_hackstate_i1() nounwind {
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entry:
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%tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16
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ret i32 %tmp2
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}
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define i16 @get_hackstate_s1() signext nounwind {
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entry:
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%tmp2 = load i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16
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ret i16 %tmp2
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}
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define i8 @get_hackstate_c6() zeroext nounwind {
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entry:
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%tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 8), align 16
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ret i8 %tmp2
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}
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define i8 @get_hackstate_c7() zeroext nounwind {
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entry:
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%tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 9), align 16
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ret i8 %tmp2
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}
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define i32 @get_hackstate_i3() nounwind {
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entry:
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%tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16
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ret i32 %tmp2
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}
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define i32 @get_hackstate_i6() nounwind {
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entry:
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%tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16
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ret i32 %tmp2
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}
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define void @set_hackstate_c1(i8 zeroext %c) nounwind {
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entry:
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store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16
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ret void
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}
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define void @set_hackstate_c2(i8 zeroext %c) nounwind {
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entry:
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store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16
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ret void
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}
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define void @set_hackstate_c3(i8 zeroext %c) nounwind {
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entry:
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store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16
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ret void
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}
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define void @set_hackstate_i1(i32 %i) nounwind {
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entry:
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store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 16
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ret void
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}
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define void @set_hackstate_s1(i16 signext %s) nounwind {
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entry:
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store i16 %s, i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16
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ret void
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}
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define void @set_hackstate_i3(i32 %i) nounwind {
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entry:
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store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 10), align 16
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ret void
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}
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define void @set_hackstate_i6(i32 %i) nounwind {
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entry:
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store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16
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ret void
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}
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