mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7c82e6a32a
intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
725 B
LLVM
22 lines
725 B
LLVM
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
|
|
; Tests vclz and vcnt
|
|
|
|
define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
|
|
;CHECK: @vclz16
|
|
%tmp1 = load <4 x i16>* %A
|
|
%tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
|
|
;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
|
|
ret <4 x i16> %tmp2
|
|
}
|
|
|
|
define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
|
|
;CHECK: @vcnt8
|
|
%tmp1 = load <8 x i8>* %A
|
|
%tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
|
|
;CHECK: call <8 x i8> @llvm.ctpop.v8i8(<8 x i8>
|
|
ret <8 x i8> %tmp2
|
|
}
|
|
|
|
declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
|
|
declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
|