mirror of
https://github.com/c64scene-ar/llvm-6502.git
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74feef261a
shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
1.4 KiB
LLVM
74 lines
1.4 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 > %t
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; RUN: grep rol %t | count 3
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; RUN: grep ror %t | count 1
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; RUN: grep shld %t | count 2
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; RUN: grep shrd %t | count 2
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define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = shl i32 %x, %z
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%1 = sub i32 32, %z
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%2 = lshr i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = shl i32 %y, %z
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%1 = sub i32 32, %z
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%2 = lshr i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = lshr i32 %x, %z
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%1 = sub i32 32, %z
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%2 = shl i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = lshr i32 %y, %z
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%1 = sub i32 32, %z
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%2 = shl i32 %x, %1
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%3 = or i32 %2, %0
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ret i32 %3
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}
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define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = lshr i32 %x, 25
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%1 = shl i32 %x, 7
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%2 = or i32 %0, %1
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ret i32 %2
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}
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define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = shl i32 %y, 7
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%1 = lshr i32 %x, 25
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%2 = or i32 %0, %1
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ret i32 %2
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}
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define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = lshr i32 %x, 7
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%1 = shl i32 %x, 25
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%2 = or i32 %0, %1
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ret i32 %2
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}
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define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%0 = lshr i32 %y, 7
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%1 = shl i32 %x, 25
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%2 = or i32 %0, %1
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ret i32 %2
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}
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