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llvm-6502/test/CodeGen/Mips/mips64ext.ll
Daniel Sanders 0543dab791 [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 tests with -mcpu=mips4 as a starting point
Summary:
Two exceptions to this:
  test/CodeGen/Mips/octeon.ll
  test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64

One test is altered for MIPS-IV:
  test/CodeGen/Mips/mips64countleading.ll
    Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
    that dclo/dclz are not emitted.

Four tests fail and are not in this patch:
  test/CodeGen/Mips/abicalls.ll
  test/CodeGen/Mips/fcopysign-f32-f64.ll
  test/CodeGen/Mips/fcopysign.ll
  test/CodeGen/Mips/stack-alignment.ll

Depends on D3343

Reviewers: matheusalmeida, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3344

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206185 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 16:00:28 +00:00

28 lines
678 B
LLVM

; RUN: llc < %s -march=mips64el -mcpu=mips4 -mattr=n64 | FileCheck %s
; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
define i64 @zext64_32(i32 %a) nounwind readnone {
entry:
; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 32
; CHECK: dsrl ${{[0-9]+}}, $[[R1]], 32
%add = add i32 %a, 2
%conv = zext i32 %add to i64
ret i64 %conv
}
define i64 @sext64_32(i32 %a) nounwind readnone {
entry:
; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0
%conv = sext i32 %a to i64
ret i64 %conv
}
define i64 @i64_float(float %f) nounwind readnone {
entry:
; CHECK: trunc.l.s
%conv = fptosi float %f to i64
ret i64 %conv
}