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https://github.com/c64scene-ar/llvm-6502.git
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4a5a8949cd
First code from the Mips16 compiler. Includes trivial test program. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157408 91177308-0d34-0410-b5e6-96231b3b80d8
632 lines
17 KiB
TableGen
632 lines
17 KiB
TableGen
//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe MIPS instructions format
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//
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// CPU INSTRUCTION FORMATS
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//
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// funct or f Function field
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//
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// immediate 4-,5-,8- or 11-bit immediate, branch displacemen, or
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// or imm address displacement
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//
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// op 5-bit major operation code
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//
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// rx 3-bit source or destination register
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//
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// ry 3-bit source or destination register
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//
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// rz 3-bit source or destination register
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//
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// sa 3- or 5-bit shift amount
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is part of the
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// ad-hoc solution used to emit machine instruction encodings by our machine
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// code emitter.
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//
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class Format16<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo16 : Format16<0>;
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def FrmI16 : Format16<1>;
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def FrmRI16 : Format16<2>;
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def FrmRR16 : Format16<3>;
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def FrmRRI16 : Format16<4>;
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def FrmRRR16 : Format16<5>;
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def FrmRRI_A16 : Format16<6>;
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def FrmSHIFT16 : Format16<7>;
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def FrmI8_TYPE16 : Format16<8>;
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def FrmI8_MOVR3216 : Format16<9>;
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def FrmI8_MOV32R16 : Format16<10>;
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def FrmI8_SVRS16 : Format16<11>;
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def FrmJAL16 : Format16<12>;
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def FrmJALX16 : Format16<13>;
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def FrmEXT_I16 : Format16<14>;
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def FrmASMACRO16 : Format16<15>;
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def FrmEXT_RI16 : Format16<16>;
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def FrmEXT_RRI16 : Format16<17>;
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def FrmEXT_RRI_A16 : Format16<18>;
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def FrmEXT_SHIFT16 : Format16<19>;
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def FrmEXT_I816 : Format16<20>;
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def FrmEXT_I8_SVRS16 : Format16<21>;
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def FrmOther16 : Format16<22>; // Instruction w/ a custom format
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// Generic Mips 16 Format
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class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>: Instruction
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{
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field bits<16> Inst;
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Format16 Form = f;
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let Namespace = "Mips";
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bits<5> Opcode = 0;
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// Top 6 bits are the 'opcode' field
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let Inst{15-11} = Opcode;
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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//
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// Attributes specific to Mips instructions...
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//
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bits<5> FormBits = Form.Value;
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{4-0} = FormBits;
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}
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//
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// TBD. Maybe MipsInst16 and Mips16_EXTEND should be derived from a single
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// base class
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//
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class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>: Instruction
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{
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field bits<32> Inst;
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Format16 Form = f;
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let Namespace = "Mips";
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bits<5> Opcode = 0;
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bits<5> extend;
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// Top 6 bits are the 'opcode' field
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let Inst{31-27} = extend;
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let Inst{15-11} = Opcode;
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Itinerary = itin;
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//
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// Attributes specific to Mips instructions...
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//
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bits<5> FormBits = Form.Value;
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// TSFlags layout should be kept in sync with MipsInstrInfo.h.
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let TSFlags{4-0} = FormBits;
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}
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// Mips Pseudo Instructions Format
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class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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//===----------------------------------------------------------------------===//
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// Format I instruction class in Mips : <|opcode|immediate|>
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//===----------------------------------------------------------------------===//
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class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: MipsInst16<outs, ins, asmstr, pattern,
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itin, FrmI16>
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{
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bits<11> imm11;
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let Opcode = op;
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let Inst{10-0} = imm11;
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}
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//===----------------------------------------------------------------------===//
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// Format RI instruction class in Mips : <|opcode|rx|immed|>
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//===----------------------------------------------------------------------===//
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class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
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{
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bits<3> rx;
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bits<8> imm8;
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let Opcode = op;
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let Inst{10-8} = rx;
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let Inst{7-0} = imm8;
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}
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//===----------------------------------------------------------------------===//
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// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
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//===----------------------------------------------------------------------===//
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class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<5> funct;
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let Opcode = 0b11101;
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let funct = _funct;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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// Format RRI instruction class in Mips : <|opcode|rx|ry|immed|>
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//===----------------------------------------------------------------------===//
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class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<5> imm5;
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let Opcode = op;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = imm5;
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}
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//===----------------------------------------------------------------------===//
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// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
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//===----------------------------------------------------------------------===//
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class FRRR16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<3> rz;
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bits<2> f;
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let Opcode = op;
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let f = _f;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-2} = rz;
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let Inst{1-0} = f;
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}
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//===----------------------------------------------------------------------===//
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// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|immed|>
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//===----------------------------------------------------------------------===//
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class FRRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<1> f;
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bits<4> imm4;
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let Opcode = op;
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let f = _f;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4} = f;
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let Inst{3-0} = imm4;
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}
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//===----------------------------------------------------------------------===//
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// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
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//===----------------------------------------------------------------------===//
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class FSHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<3> sa;
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bits<2> f;
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let Opcode = op;
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let f = _f;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-2} = sa;
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let Inst{1-0} = f;
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}
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//===----------------------------------------------------------------------===//
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// Format i8 instruction class in Mips : <|opcode|funct|immed>
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//===----------------------------------------------------------------------===//
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class FI816<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
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{
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bits<3> func;
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bits<8> immed8;
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let Opcode = op;
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let func = _func;
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let Inst{10-8} = func;
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let Inst{7-0} = immed8;
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}
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//===----------------------------------------------------------------------===//
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// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
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//===----------------------------------------------------------------------===//
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class FI8_MOVR3216<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
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{
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bits<3> func;
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bits<4> ry;
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bits<4> r32;
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let Opcode = op;
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let func = _func;
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let Inst{10-8} = func;
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let Inst{7-4} = ry;
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let Inst{3-0} = r32;
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}
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//===----------------------------------------------------------------------===//
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// Format i8_MOV32R instruction class in Mips : <|opcode|func|ry|r32>
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//===----------------------------------------------------------------------===//
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class FI8_MOV32R16<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
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{
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bits<3> func;
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bits<5> r32;
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bits<3> rz;
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let Opcode = op;
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let func = _func;
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let Inst{10-8} = func;
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let Inst{7-5} = r32{2-0};
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let Inst{4-3} = r32{4-3};
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let Inst{2-0} = rz;
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}
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//===----------------------------------------------------------------------===//
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// Format i8_SVRS instruction class in Mips :
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// <|opcode|svrs|s|ra|s0|s1|framesize>
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//===----------------------------------------------------------------------===//
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class FI8_SVRS16<bits<5> op, bits<3> _SVRS, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
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{
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bits<3> SVRS;
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bits<1> s;
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bits<1> ra;
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bits<1> s0;
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bits<1> s1;
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bits<4> framesize;
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let Opcode = op;
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let SVRS = _SVRS;
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let Inst{10-8} = SVRS;
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let Inst{7} = s;
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let Inst{6} = ra;
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let Inst{5} = s0;
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let Inst{4} = s1;
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let Inst{3-0} = framesize;
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}
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//===----------------------------------------------------------------------===//
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// Format JAL instruction class in Mips16 :
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// <|opcode|svrs|s|ra|s0|s1|framesize>
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//===----------------------------------------------------------------------===//
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class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmJAL16>
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{
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bits<1> X;
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bits<26> immed26;
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let Opcode = op;
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let X = _X;
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let Inst{26} = X;
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let Inst{25-21} = immed26{20-16};
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let Inst{20-16} = immed26{25-21};
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let Inst{15-0} = immed26{15-0};
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-I instruction class in Mips16 :
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// <|opcode|immed10:5|immed15:1|op|0|0|0|0|0|0|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_I16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
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{
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bits<16> immed16;
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bits<5> eop;
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let Opcode = op;
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let eop = _eop;
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let Inst{26-21} = immed16{10-5};
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let Inst{20-16} = immed16{15-11};
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let Inst{15-11} = eop;
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let Inst{10-5} = 0;
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let Inst{4-0} = immed16{4-0};
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}
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//===----------------------------------------------------------------------===//
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// Format ASMACRO instruction class in Mips16 :
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// <EXTEND|select|p4|p3|RRR|p2|p1|p0>
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//===----------------------------------------------------------------------===//
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class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmASMACRO16>
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{
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bits<3> select;
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bits<3> p4;
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bits<5> p3;
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bits<5> RRR;
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bits<3> p2;
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bits<3> p1;
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bits<5> p0;
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let Opcode = op;
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let Inst{26-24} = select;
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let Inst{23-21} = p4;
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let Inst{20-16} = p3;
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let Inst{15-11} = RRR;
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let Inst{10-8} = p2;
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let Inst{7-5} = p1;
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let Inst{4-0} = p0;
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-RI instruction class in Mips16 :
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// <|opcode|immed10:5|immed15:11|op|rx|0|0|0|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_RI16>
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{
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bits<16> immed16;
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bits<5> eop;
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bits<3> rx;
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let Opcode = op;
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let eop = _eop;
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let Inst{26-21} = immed16{10-5};
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let Inst{20-16} = immed16{15-11};
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let Inst{15-11} = eop;
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let Inst{10-8} = rx;
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let Inst{7-5} = 0;
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let Inst{4-0} = immed16{4-0};
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-RRI instruction class in Mips16 :
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// <|opcode|immed10:5|immed15:11|op|rx|ry|immed4:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RRI16<bits<5> op, bits<5> _eop, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_RRI16>
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{
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bits<16> immed16;
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bits<5> eop;
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bits<3> rx;
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bits<3> ry;
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let Opcode = op;
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let eop = _eop;
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let Inst{26-21} = immed16{10-5};
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let Inst{20-16} = immed16{15-11};
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let Inst{15-11} = eop;
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let Inst{10-8} = rx;
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let Inst{7-5} = ry;
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let Inst{4-0} = immed16{4-0};
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-RRI-A instruction class in Mips16 :
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// <|opcode|immed10:4|immed14:11|RRI-A|rx|ry|f|immed3:0>
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//===----------------------------------------------------------------------===//
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class FEXT_RRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
|
FrmEXT_RRI_A16>
|
|
{
|
|
bits<15> immed15;
|
|
bits<5> RRI_A;
|
|
bits<3> rx;
|
|
bits<3> ry;
|
|
bits<1> f;
|
|
|
|
let Opcode = op;
|
|
let f = _f;
|
|
|
|
let Inst{26-20} = immed15{10-4};
|
|
let Inst{19-16} = immed15{14-11};
|
|
let Inst{15-11} = RRI_A;
|
|
let Inst{10-8} = rx;
|
|
let Inst{7-5} = ry;
|
|
let Inst{4} = f;
|
|
let Inst{3-0} = immed15{3-0};
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Format EXT-SHIFT instruction class in Mips16 :
|
|
// <|opcode|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
|
|
list<dag> pattern, InstrItinClass itin>:
|
|
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
|
FrmEXT_SHIFT16>
|
|
{
|
|
bits<6> sa6;
|
|
bits<5> shift;
|
|
bits<3> rx;
|
|
bits<3> ry;
|
|
bits<2> f;
|
|
|
|
let Opcode = op;
|
|
let f = _f;
|
|
|
|
let Inst{26-22} = sa6{4-0};
|
|
let Inst{21} = sa6{5};
|
|
let Inst{20-16} = 0;
|
|
let Inst{15-11} = shift;
|
|
let Inst{10-8} = rx;
|
|
let Inst{7-5} = ry;
|
|
let Inst{4-2} = 0;
|
|
let Inst{1-0} = f;
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Format EXT-I8 instruction class in Mips16 :
|
|
// <|opcode|immed10:5|immed15:11|I8|funct|0|immed4:0>
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FEXT_I816<bits<5> op, bits<3> _funct, dag outs, dag ins, string asmstr,
|
|
list<dag> pattern, InstrItinClass itin>:
|
|
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
|
FrmEXT_I816>
|
|
{
|
|
bits<16> immed16;
|
|
bits<5> I8;
|
|
bits<3> funct;
|
|
|
|
let Opcode = op;
|
|
let funct = _funct;
|
|
|
|
let Inst{26-21} = immed16{10-5};
|
|
let Inst{20-16} = immed16{15-11};
|
|
let Inst{15-11} = I8;
|
|
let Inst{10-8} = funct;
|
|
let Inst{7-5} = 0;
|
|
let Inst{4-0} = immed16{4-0};
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Format EXT-I8_SVRS instruction class in Mips16 :
|
|
// <|opcode|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class FEXT_I8_SVRS16<bits<5> op, dag outs, dag ins, string asmstr,
|
|
list<dag> pattern, InstrItinClass itin>:
|
|
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
|
FrmI8_SVRS16>
|
|
{
|
|
bits<3> xsregs;
|
|
bits<8> framesize;
|
|
bits<3> aregs;
|
|
bits<5> I8;
|
|
bits<3> SVRS;
|
|
bits<1> s;
|
|
bits<1> ra;
|
|
bits<1> s0;
|
|
bits<1> s1;
|
|
|
|
let Opcode = op;
|
|
|
|
let Inst{26-24} = xsregs;
|
|
let Inst{23-20} = framesize{7-4};
|
|
let Inst{19} = 0;
|
|
let Inst{18-16} = aregs;
|
|
let Inst{15-11} = I8;
|
|
let Inst{10-8} = SVRS;
|
|
let Inst{7} = s;
|
|
let Inst{6} = ra;
|
|
let Inst{5} = s0;
|
|
let Inst{4} = s1;
|
|
let Inst{3-0} = framesize{3-0};
|
|
|
|
|
|
}
|
|
|
|
|
|
|