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https://github.com/c64scene-ar/llvm-6502.git
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6660ed5f2f
The fast register allocator is not supposed to work in the optimizing pipeline. It doesn't make sense to compute live intervals, run full copy coalescing, and then run RAFast. Fast register allocation in the optimizing pipeline is better done by RABasic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158242 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
2.0 KiB
LLVM
49 lines
2.0 KiB
LLVM
; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
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; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s
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; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s
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; The 1st, 2nd, 3rd and 5th registers must all be different. The registers
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; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
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; operand.
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;
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; CHECK: 1st=[[A1:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK: 2nd=[[A2:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK-NOT: [[A2]]
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; CHECK: 3rd=[[A3:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK-NOT: [[A2]]
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; CHECK-NOT: [[A3]]
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; CHECK: 5th=[[A5:%...]]
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; CHECK-NOT: [[A1]]
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; CHECK-NOT: [[A5]]
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; CHECK: =4th
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; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.
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; CHECK: 1%e[[S1:.]]x
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; CHECK: 5%e[[S5:.]]x
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; CHECK-NOT: %[[S1]]
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; CHECK-NOT: %[[S5]]
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin8"
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%struct.foo = type { i32, i32, i8* }
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define i32 @get(%struct.foo* %c, i8* %state) nounwind {
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entry:
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%0 = getelementptr %struct.foo* %c, i32 0, i32 0 ; <i32*> [#uses=2]
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%1 = getelementptr %struct.foo* %c, i32 0, i32 1 ; <i32*> [#uses=2]
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%2 = getelementptr %struct.foo* %c, i32 0, i32 2 ; <i8**> [#uses=2]
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%3 = load i32* %0, align 4 ; <i32> [#uses=1]
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%4 = load i32* %1, align 4 ; <i32> [#uses=1]
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%5 = load i8* %state, align 1 ; <i8> [#uses=1]
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%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
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%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
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%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
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store i32 %asmresult1, i32* %0
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%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
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store i32 %asmresult2, i32* %1
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ret i32 %asmresult
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}
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