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17c836c4b5
* Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
367 B
LLVM
15 lines
367 B
LLVM
; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s
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; PR6679
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define float @foo(float* %col.2.0) {
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; CHECK: fucomp
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; CHECK-NOT: fucompi
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; CHECK: j
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; CHECK-NOT: fcmov
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%tmp = load float* %col.2.0
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%tmp16 = fcmp olt float %tmp, 0.000000e+00
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%tmp20 = fsub float -0.000000e+00, %tmp
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%iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp
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ret float %iftmp.2.0
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}
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