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#includes in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
885 lines
26 KiB
C++
885 lines
26 KiB
C++
//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMSubtarget.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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using namespace llvm;
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namespace {
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struct ARMOperand;
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// The shift types for register controlled shifts in arm memory addressing
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enum ShiftType {
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Lsl,
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Lsr,
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Asr,
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Ror,
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Rrx
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};
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class ARMAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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TargetMachine &TM;
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private:
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
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bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
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bool ParseMemory(OwningPtr<ARMOperand> &Op);
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bool ParseMemoryOffsetReg(bool &Negative,
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bool &OffsetRegShifted,
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enum ShiftType &ShiftType,
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const MCExpr *&ShiftAmount,
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const MCExpr *&Offset,
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bool &OffsetIsReg,
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int &OffsetRegNum,
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SMLoc &E);
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bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
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bool ParseOperand(OwningPtr<ARMOperand> &Op);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveThumb(SMLoc L);
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bool ParseDirectiveThumbFunc(SMLoc L);
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bool ParseDirectiveCode(SMLoc L);
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bool ParseDirectiveSyntax(SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out) {
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MCInst Inst;
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unsigned ErrorInfo;
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if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) {
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Out.EmitInstruction(Inst);
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return false;
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}
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// FIXME: We should give nicer diagnostics about the exact failure.
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Error(IDLoc, "unrecognized instruction");
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return true;
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}
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/// @name Auto-generated Match Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "ARMGenAsmMatcher.inc"
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/// }
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public:
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ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
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: TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
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virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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/// ARMOperand - Instances of this class represent a parsed ARM machine
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/// instruction.
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struct ARMOperand : public MCParsedAsmOperand {
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private:
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ARMOperand() {}
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public:
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enum KindTy {
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CondCode,
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Immediate,
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Memory,
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Register,
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Token
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} Kind;
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SMLoc StartLoc, EndLoc;
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union {
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struct {
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ARMCC::CondCodes Val;
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} CC;
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNum;
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bool Writeback;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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// This is for all forms of ARM address expressions
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struct {
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unsigned BaseRegNum;
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unsigned OffsetRegNum; // used when OffsetIsReg is true
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const MCExpr *Offset; // used when OffsetIsReg is false
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const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
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enum ShiftType ShiftType; // used when OffsetRegShifted is true
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unsigned
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OffsetRegShifted : 1, // only used when OffsetIsReg is true
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Preindexed : 1,
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Postindexed : 1,
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OffsetIsReg : 1,
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Negative : 1, // only used when OffsetIsReg is true
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Writeback : 1;
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} Mem;
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};
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//ARMOperand(KindTy K, SMLoc S, SMLoc E)
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// : Kind(K), StartLoc(S), EndLoc(E) {}
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ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
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Kind = o.Kind;
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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switch (Kind) {
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case CondCode:
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CC = o.CC;
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break;
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case Token:
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Tok = o.Tok;
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break;
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case Register:
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Reg = o.Reg;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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case Memory:
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Mem = o.Mem;
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break;
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}
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}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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ARMCC::CondCodes getCondCode() const {
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assert(Kind == CondCode && "Invalid access!");
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return CC.Val;
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNum;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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bool isCondCode() const { return Kind == CondCode; }
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bool isImm() const { return Kind == Immediate; }
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bool isReg() const { return Kind == Register; }
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bool isToken() const {return Kind == Token; }
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible.
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addCondCodeOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
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// FIXME: What belongs here?
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Inst.addOperand(MCOperand::CreateReg(0));
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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virtual void dump(raw_ostream &OS) const;
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static void CreateCondCode(OwningPtr<ARMOperand> &Op, ARMCC::CondCodes CC,
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SMLoc S) {
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Op.reset(new ARMOperand);
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Op->Kind = CondCode;
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Op->CC.Val = CC;
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Op->StartLoc = S;
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Op->EndLoc = S;
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}
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static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
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SMLoc S) {
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Op.reset(new ARMOperand);
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Op->Kind = Token;
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Op->Tok.Data = Str.data();
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Op->Tok.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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}
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static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
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bool Writeback, SMLoc S, SMLoc E) {
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Op.reset(new ARMOperand);
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Op->Kind = Register;
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Op->Reg.RegNum = RegNum;
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Op->Reg.Writeback = Writeback;
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Op->StartLoc = S;
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Op->EndLoc = E;
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}
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static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
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SMLoc S, SMLoc E) {
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Op.reset(new ARMOperand);
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Op->Kind = Immediate;
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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}
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static void CreateMem(OwningPtr<ARMOperand> &Op,
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unsigned BaseRegNum, bool OffsetIsReg,
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const MCExpr *Offset, unsigned OffsetRegNum,
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bool OffsetRegShifted, enum ShiftType ShiftType,
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const MCExpr *ShiftAmount, bool Preindexed,
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bool Postindexed, bool Negative, bool Writeback,
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SMLoc S, SMLoc E) {
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Op.reset(new ARMOperand);
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Op->Kind = Memory;
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Op->Mem.BaseRegNum = BaseRegNum;
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Op->Mem.OffsetIsReg = OffsetIsReg;
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Op->Mem.Offset = Offset;
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Op->Mem.OffsetRegNum = OffsetRegNum;
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Op->Mem.OffsetRegShifted = OffsetRegShifted;
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Op->Mem.ShiftType = ShiftType;
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Op->Mem.ShiftAmount = ShiftAmount;
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Op->Mem.Preindexed = Preindexed;
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Op->Mem.Postindexed = Postindexed;
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Op->Mem.Negative = Negative;
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Op->Mem.Writeback = Writeback;
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Op->StartLoc = S;
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Op->EndLoc = E;
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}
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};
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} // end anonymous namespace.
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void ARMOperand::dump(raw_ostream &OS) const {
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switch (Kind) {
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case CondCode:
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OS << ARMCondCodeToString(getCondCode());
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break;
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case Immediate:
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getImm()->print(OS);
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break;
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case Memory:
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OS << "<memory>";
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break;
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case Register:
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OS << "<register " << getReg() << ">";
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break;
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case Token:
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OS << "'" << getToken() << "'";
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break;
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}
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}
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/// @name Auto-generated Match Functions
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/// {
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static unsigned MatchRegisterName(StringRef Name);
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/// }
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/// Try to parse a register name. The token must be an Identifier when called,
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/// and if it is a register name a Reg operand is created, the token is eaten
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/// and false is returned. Else true is returned and no token is eaten.
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/// TODO this is likely to change to allow different register types and or to
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/// parse for a specific register type.
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bool ARMAsmParser::MaybeParseRegister
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(OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
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SMLoc S, E;
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const AsmToken &Tok = Parser.getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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int RegNum;
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RegNum = MatchRegisterName(Tok.getString());
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if (RegNum == -1)
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return true;
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S = Tok.getLoc();
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Parser.Lex(); // Eat identifier token.
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E = Parser.getTok().getLoc();
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bool Writeback = false;
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if (ParseWriteBack) {
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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E = ExclaimTok.getLoc();
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Writeback = true;
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Parser.Lex(); // Eat exclaim token
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}
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}
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ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
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return false;
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}
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/// Parse a register list, return false if successful else return true or an
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/// error. The first token must be a '{' when called.
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bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
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SMLoc S, E;
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assert(Parser.getTok().is(AsmToken::LCurly) &&
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"Token is not an Left Curly Brace");
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S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat left curly brace token.
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const AsmToken &RegTok = Parser.getTok();
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SMLoc RegLoc = RegTok.getLoc();
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if (RegTok.isNot(AsmToken::Identifier))
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return Error(RegLoc, "register expected");
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int RegNum = MatchRegisterName(RegTok.getString());
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if (RegNum == -1)
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return Error(RegLoc, "register expected");
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Parser.Lex(); // Eat identifier token.
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unsigned RegList = 1 << RegNum;
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int HighRegNum = RegNum;
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// TODO ranges like "{Rn-Rm}"
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while (Parser.getTok().is(AsmToken::Comma)) {
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Parser.Lex(); // Eat comma token.
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const AsmToken &RegTok = Parser.getTok();
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SMLoc RegLoc = RegTok.getLoc();
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if (RegTok.isNot(AsmToken::Identifier))
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return Error(RegLoc, "register expected");
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int RegNum = MatchRegisterName(RegTok.getString());
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if (RegNum == -1)
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return Error(RegLoc, "register expected");
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if (RegList & (1 << RegNum))
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Warning(RegLoc, "register duplicated in register list");
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else if (RegNum <= HighRegNum)
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Warning(RegLoc, "register not in ascending order in register list");
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RegList |= 1 << RegNum;
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HighRegNum = RegNum;
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Parser.Lex(); // Eat identifier token.
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}
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const AsmToken &RCurlyTok = Parser.getTok();
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if (RCurlyTok.isNot(AsmToken::RCurly))
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return Error(RCurlyTok.getLoc(), "'}' expected");
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E = RCurlyTok.getLoc();
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Parser.Lex(); // Eat left curly brace token.
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return false;
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}
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/// Parse an arm memory expression, return false if successful else return true
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/// or an error. The first token must be a '[' when called.
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/// TODO Only preindexing and postindexing addressing are started, unindexed
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/// with option, etc are still to do.
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bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
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SMLoc S, E;
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assert(Parser.getTok().is(AsmToken::LBrac) &&
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"Token is not an Left Bracket");
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S = Parser.getTok().getLoc();
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Parser.Lex(); // Eat left bracket token.
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const AsmToken &BaseRegTok = Parser.getTok();
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if (BaseRegTok.isNot(AsmToken::Identifier))
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return Error(BaseRegTok.getLoc(), "register expected");
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if (MaybeParseRegister(Op, false))
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return Error(BaseRegTok.getLoc(), "register expected");
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int BaseRegNum = Op->getReg();
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bool Preindexed = false;
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bool Postindexed = false;
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bool OffsetIsReg = false;
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bool Negative = false;
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bool Writeback = false;
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// First look for preindexed address forms, that is after the "[Rn" we now
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// have to see if the next token is a comma.
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const AsmToken &Tok = Parser.getTok();
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if (Tok.is(AsmToken::Comma)) {
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Preindexed = true;
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Parser.Lex(); // Eat comma token.
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int OffsetRegNum;
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bool OffsetRegShifted;
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enum ShiftType ShiftType;
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const MCExpr *ShiftAmount;
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const MCExpr *Offset;
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if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
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Offset, OffsetIsReg, OffsetRegNum, E))
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return true;
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const AsmToken &RBracTok = Parser.getTok();
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if (RBracTok.isNot(AsmToken::RBrac))
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return Error(RBracTok.getLoc(), "']' expected");
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E = RBracTok.getLoc();
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Parser.Lex(); // Eat right bracket token.
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const AsmToken &ExclaimTok = Parser.getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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E = ExclaimTok.getLoc();
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Writeback = true;
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Parser.Lex(); // Eat exclaim token
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}
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ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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OffsetRegShifted, ShiftType, ShiftAmount,
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Preindexed, Postindexed, Negative, Writeback, S, E);
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return false;
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}
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// The "[Rn" we have so far was not followed by a comma.
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else if (Tok.is(AsmToken::RBrac)) {
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// This is a post indexing addressing forms, that is a ']' follows after
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// the "[Rn".
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Postindexed = true;
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Writeback = true;
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E = Tok.getLoc();
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Parser.Lex(); // Eat right bracket token.
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int OffsetRegNum = 0;
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bool OffsetRegShifted = false;
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enum ShiftType ShiftType;
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const MCExpr *ShiftAmount;
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const MCExpr *Offset;
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const AsmToken &NextTok = Parser.getTok();
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if (NextTok.isNot(AsmToken::EndOfStatement)) {
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if (NextTok.isNot(AsmToken::Comma))
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return Error(NextTok.getLoc(), "',' expected");
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Parser.Lex(); // Eat comma token.
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if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
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ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
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E))
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return true;
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}
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ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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OffsetRegShifted, ShiftType, ShiftAmount,
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Preindexed, Postindexed, Negative, Writeback, S, E);
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
|
|
/// we will parse the following (were +/- means that a plus or minus is
|
|
/// optional):
|
|
/// +/-Rm
|
|
/// +/-Rm, shift
|
|
/// #offset
|
|
/// we return false on success or an error otherwise.
|
|
bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
|
|
bool &OffsetRegShifted,
|
|
enum ShiftType &ShiftType,
|
|
const MCExpr *&ShiftAmount,
|
|
const MCExpr *&Offset,
|
|
bool &OffsetIsReg,
|
|
int &OffsetRegNum,
|
|
SMLoc &E) {
|
|
OwningPtr<ARMOperand> Op;
|
|
Negative = false;
|
|
OffsetRegShifted = false;
|
|
OffsetIsReg = false;
|
|
OffsetRegNum = -1;
|
|
const AsmToken &NextTok = Parser.getTok();
|
|
E = NextTok.getLoc();
|
|
if (NextTok.is(AsmToken::Plus))
|
|
Parser.Lex(); // Eat plus token.
|
|
else if (NextTok.is(AsmToken::Minus)) {
|
|
Negative = true;
|
|
Parser.Lex(); // Eat minus token
|
|
}
|
|
// See if there is a register following the "[Rn," or "[Rn]," we have so far.
|
|
const AsmToken &OffsetRegTok = Parser.getTok();
|
|
if (OffsetRegTok.is(AsmToken::Identifier)) {
|
|
OffsetIsReg = !MaybeParseRegister(Op, false);
|
|
if (OffsetIsReg) {
|
|
E = Op->getEndLoc();
|
|
OffsetRegNum = Op->getReg();
|
|
}
|
|
}
|
|
// If we parsed a register as the offset then their can be a shift after that
|
|
if (OffsetRegNum != -1) {
|
|
// Look for a comma then a shift
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat comma token.
|
|
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (ParseShift(ShiftType, ShiftAmount, E))
|
|
return Error(Tok.getLoc(), "shift expected");
|
|
OffsetRegShifted = true;
|
|
}
|
|
}
|
|
else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
|
|
// Look for #offset following the "[Rn," or "[Rn],"
|
|
const AsmToken &HashTok = Parser.getTok();
|
|
if (HashTok.isNot(AsmToken::Hash))
|
|
return Error(HashTok.getLoc(), "'#' expected");
|
|
|
|
Parser.Lex(); // Eat hash token.
|
|
|
|
if (getParser().ParseExpression(Offset))
|
|
return true;
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// ParseShift as one of these two:
|
|
/// ( lsl | lsr | asr | ror ) , # shift_amount
|
|
/// rrx
|
|
/// and returns true if it parses a shift otherwise it returns false.
|
|
bool ARMAsmParser::ParseShift(ShiftType &St,
|
|
const MCExpr *&ShiftAmount,
|
|
SMLoc &E) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Identifier))
|
|
return true;
|
|
StringRef ShiftName = Tok.getString();
|
|
if (ShiftName == "lsl" || ShiftName == "LSL")
|
|
St = Lsl;
|
|
else if (ShiftName == "lsr" || ShiftName == "LSR")
|
|
St = Lsr;
|
|
else if (ShiftName == "asr" || ShiftName == "ASR")
|
|
St = Asr;
|
|
else if (ShiftName == "ror" || ShiftName == "ROR")
|
|
St = Ror;
|
|
else if (ShiftName == "rrx" || ShiftName == "RRX")
|
|
St = Rrx;
|
|
else
|
|
return true;
|
|
Parser.Lex(); // Eat shift type token.
|
|
|
|
// Rrx stands alone.
|
|
if (St == Rrx)
|
|
return false;
|
|
|
|
// Otherwise, there must be a '#' and a shift amount.
|
|
const AsmToken &HashTok = Parser.getTok();
|
|
if (HashTok.isNot(AsmToken::Hash))
|
|
return Error(HashTok.getLoc(), "'#' expected");
|
|
Parser.Lex(); // Eat hash token.
|
|
|
|
if (getParser().ParseExpression(ShiftAmount))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// Parse a arm instruction operand. For now this parses the operand regardless
|
|
/// of the mnemonic.
|
|
bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
|
|
SMLoc S, E;
|
|
|
|
switch (getLexer().getKind()) {
|
|
case AsmToken::Identifier:
|
|
if (!MaybeParseRegister(Op, true))
|
|
return false;
|
|
// This was not a register so parse other operands that start with an
|
|
// identifier (like labels) as expressions and create them as immediates.
|
|
const MCExpr *IdVal;
|
|
S = Parser.getTok().getLoc();
|
|
if (getParser().ParseExpression(IdVal))
|
|
return true;
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
ARMOperand::CreateImm(Op, IdVal, S, E);
|
|
return false;
|
|
case AsmToken::LBrac:
|
|
return ParseMemory(Op);
|
|
case AsmToken::LCurly:
|
|
return ParseRegisterList(Op);
|
|
case AsmToken::Hash:
|
|
// #42 -> immediate.
|
|
// TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
|
|
S = Parser.getTok().getLoc();
|
|
Parser.Lex();
|
|
const MCExpr *ImmVal;
|
|
if (getParser().ParseExpression(ImmVal))
|
|
return true;
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
ARMOperand::CreateImm(Op, ImmVal, S, E);
|
|
return false;
|
|
default:
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in operand");
|
|
}
|
|
}
|
|
|
|
/// Parse an arm instruction mnemonic followed by its operands.
|
|
bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
OwningPtr<ARMOperand> Op;
|
|
|
|
// Create the leading tokens for the mnemonic, split by '.' characters.
|
|
size_t Start = 0, Next = Name.find('.');
|
|
StringRef Head = Name.slice(Start, Next);
|
|
|
|
// Determine the predicate, if any.
|
|
//
|
|
// FIXME: We need a way to check whether a prefix supports predication,
|
|
// otherwise we will end up with an ambiguity for instructions that happen to
|
|
// end with a predicate name.
|
|
unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
|
|
.Case("eq", ARMCC::EQ)
|
|
.Case("ne", ARMCC::NE)
|
|
.Case("hs", ARMCC::HS)
|
|
.Case("lo", ARMCC::LO)
|
|
.Case("mi", ARMCC::MI)
|
|
.Case("pl", ARMCC::PL)
|
|
.Case("vs", ARMCC::VS)
|
|
.Case("vc", ARMCC::VC)
|
|
.Case("hi", ARMCC::HI)
|
|
.Case("ls", ARMCC::LS)
|
|
.Case("ge", ARMCC::GE)
|
|
.Case("lt", ARMCC::LT)
|
|
.Case("gt", ARMCC::GT)
|
|
.Case("le", ARMCC::LE)
|
|
.Case("al", ARMCC::AL)
|
|
.Default(~0U);
|
|
if (CC != ~0U) {
|
|
Head = Head.slice(0, Head.size() - 2);
|
|
} else
|
|
CC = ARMCC::AL;
|
|
|
|
ARMOperand::CreateToken(Op, Head, NameLoc);
|
|
Operands.push_back(Op.take());
|
|
|
|
ARMOperand::CreateCondCode(Op, ARMCC::CondCodes(CC), NameLoc);
|
|
Operands.push_back(Op.take());
|
|
|
|
// Add the remaining tokens in the mnemonic.
|
|
while (Next != StringRef::npos) {
|
|
Start = Next;
|
|
Next = Name.find('.', Start + 1);
|
|
Head = Name.slice(Start, Next);
|
|
|
|
ARMOperand::CreateToken(Op, Head, NameLoc);
|
|
Operands.push_back(Op.take());
|
|
}
|
|
|
|
// Read the remaining operands.
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
// Read the first operand.
|
|
OwningPtr<ARMOperand> Op;
|
|
if (ParseOperand(Op)) {
|
|
Parser.EatToEndOfStatement();
|
|
return true;
|
|
}
|
|
Operands.push_back(Op.take());
|
|
|
|
while (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
// Parse and remember the operand.
|
|
if (ParseOperand(Op)) {
|
|
Parser.EatToEndOfStatement();
|
|
return true;
|
|
}
|
|
Operands.push_back(Op.take());
|
|
}
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
Parser.EatToEndOfStatement();
|
|
return TokError("unexpected token in argument list");
|
|
}
|
|
Parser.Lex(); // Consume the EndOfStatement
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirective parses the arm specific directives
|
|
bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (IDVal == ".word")
|
|
return ParseDirectiveWord(4, DirectiveID.getLoc());
|
|
else if (IDVal == ".thumb")
|
|
return ParseDirectiveThumb(DirectiveID.getLoc());
|
|
else if (IDVal == ".thumb_func")
|
|
return ParseDirectiveThumbFunc(DirectiveID.getLoc());
|
|
else if (IDVal == ".code")
|
|
return ParseDirectiveCode(DirectiveID.getLoc());
|
|
else if (IDVal == ".syntax")
|
|
return ParseDirectiveSyntax(DirectiveID.getLoc());
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirectiveWord
|
|
/// ::= .word [ expression (, expression)* ]
|
|
bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
for (;;) {
|
|
const MCExpr *Value;
|
|
if (getParser().ParseExpression(Value))
|
|
return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
// FIXME: Improve diagnostic.
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveThumb
|
|
/// ::= .thumb
|
|
bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// TODO: set thumb mode
|
|
// TODO: tell the MC streamer the mode
|
|
// getParser().getStreamer().Emit???();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveThumbFunc
|
|
/// ::= .thumbfunc symbol_name
|
|
bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
|
|
return Error(L, "unexpected token in .syntax directive");
|
|
Parser.Lex(); // Consume the identifier token.
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// TODO: mark symbol as a thumb symbol
|
|
// getParser().getStreamer().Emit???();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveSyntax
|
|
/// ::= .syntax unified | divided
|
|
bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Identifier))
|
|
return Error(L, "unexpected token in .syntax directive");
|
|
StringRef Mode = Tok.getString();
|
|
if (Mode == "unified" || Mode == "UNIFIED")
|
|
Parser.Lex();
|
|
else if (Mode == "divided" || Mode == "DIVIDED")
|
|
Parser.Lex();
|
|
else
|
|
return Error(L, "unrecognized syntax mode in .syntax directive");
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// TODO tell the MC streamer the mode
|
|
// getParser().getStreamer().Emit???();
|
|
return false;
|
|
}
|
|
|
|
/// ParseDirectiveCode
|
|
/// ::= .code 16 | 32
|
|
bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
|
|
const AsmToken &Tok = Parser.getTok();
|
|
if (Tok.isNot(AsmToken::Integer))
|
|
return Error(L, "unexpected token in .code directive");
|
|
int64_t Val = Parser.getTok().getIntVal();
|
|
if (Val == 16)
|
|
Parser.Lex();
|
|
else if (Val == 32)
|
|
Parser.Lex();
|
|
else
|
|
return Error(L, "invalid operand to .code directive");
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement))
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in directive");
|
|
Parser.Lex();
|
|
|
|
// TODO tell the MC streamer the mode
|
|
// getParser().getStreamer().Emit???();
|
|
return false;
|
|
}
|
|
|
|
extern "C" void LLVMInitializeARMAsmLexer();
|
|
|
|
/// Force static initialization.
|
|
extern "C" void LLVMInitializeARMAsmParser() {
|
|
RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
|
|
RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
|
|
LLVMInitializeARMAsmLexer();
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "ARMGenAsmMatcher.inc"
|