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https://github.com/c64scene-ar/llvm-6502.git
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733681d3bd
These instructions do not indicate they are extendable or the number of bits in the extendable operand. Rename to match architected names. Add a testcase for the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218453 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
1.5 KiB
LLVM
51 lines
1.5 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate matching compare insn.
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; Function Attrs: nounwind
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define i32 @neqi(i32 %argc) #0 {
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entry:
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%p = alloca i8, align 1
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%0 = tail call i1 @llvm.hexagon.C4.cmpneqi(i32 %argc, i32 512)
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%conv = zext i1 %0 to i8
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store volatile i8 %conv, i8* %p, align 1
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%p.0.p.0. = load volatile i8* %p, align 1
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%conv1 = zext i8 %p.0.p.0. to i32
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ret i32 %conv1
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}
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; CHECK: p{{[0-3]}}{{ *}} = !cmp.eq(r{{[0-9]+}}, ##512)
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; Function Attrs: nounwind readnone
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declare i1 @llvm.hexagon.C4.cmpneqi(i32, i32) #1
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; Function Attrs: nounwind
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define i32 @ngti(i32 %argc) #0 {
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entry:
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%p = alloca i8, align 1
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%0 = tail call i1 @llvm.hexagon.C4.cmpltei(i32 %argc, i32 4)
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%conv = zext i1 %0 to i8
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store volatile i8 %conv, i8* %p, align 1
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%p.0.p.0. = load volatile i8* %p, align 1
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%conv1 = zext i8 %p.0.p.0. to i32
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ret i32 %conv1
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}
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; CHECK: p{{[0-3]}}{{ *}} = !cmp.gt(r{{[0-9]+}}, #4)
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; Function Attrs: nounwind readnone
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declare i1 @llvm.hexagon.C4.cmpltei(i32, i32) #1
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; Function Attrs: nounwind
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define i32 @ngtui(i32 %argc) #0 {
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entry:
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%p = alloca i8, align 1
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%0 = tail call i1 @llvm.hexagon.C4.cmplteui(i32 %argc, i32 4)
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%conv = zext i1 %0 to i8
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store volatile i8 %conv, i8* %p, align 1
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%p.0.p.0. = load volatile i8* %p, align 1
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%conv1 = zext i8 %p.0.p.0. to i32
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ret i32 %conv1
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}
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; CHECK: p{{[0-3]}}{{ *}} = !cmp.gtu(r{{[0-9]+}}, #4)
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; Function Attrs: nounwind readnone
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declare i1 @llvm.hexagon.C4.cmplteui(i32, i32) #1
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