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https://github.com/c64scene-ar/llvm-6502.git
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c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
3.1 KiB
C++
91 lines
3.1 KiB
C++
//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIINSTRINFO_H
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#define SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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namespace llvm {
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class SIInstrInfo : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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public:
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explicit SIInstrInfo(AMDGPUTargetMachine &tm);
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const SIRegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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/// \returns the encoding type of this instruction.
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unsigned getEncodingType(const MachineInstr &MI) const;
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/// \returns the size of this instructions encoding in number of bytes.
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unsigned getEncodingBytes(const MachineInstr &MI) const;
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virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const;
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virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
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virtual bool isMov(unsigned Opcode) const;
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virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
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virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
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virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
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virtual unsigned calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const;
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virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
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unsigned SourceReg) const;
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virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
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virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address,
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unsigned OffsetReg) const;
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virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
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};
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} // End namespace llvm
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namespace SIInstrFlags {
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enum Flags {
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// First 4 bits are the instruction encoding
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VM_CNT = 1 << 4,
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EXP_CNT = 1 << 5,
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LGKM_CNT = 1 << 6
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};
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}
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#endif //SIINSTRINFO_H
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