llvm-6502/test/CodeGen
Chandler Carruth 07ef8904ad [x86] Now that the new vector shuffle legality is enabled and everything
is going well, remove the flag and the code for the old legality tests.

This is the first step toward removing the entire old vector shuffle
lowering. *Much* more code to delete coming up next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229963 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-20 03:59:35 +00:00
..
AArch64
ARM [ARM] Re-re-apply VLD1/VST1 base-update combine. 2015-02-19 23:52:41 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation 2015-02-20 02:15:36 +00:00
MSP430
NVPTX
PowerPC This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions. 2015-02-18 16:21:46 +00:00
R600 R600/SI: Add missing offset operand to buffer bothen 2015-02-18 02:04:38 +00:00
SPARC
SystemZ [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86 [x86] Now that the new vector shuffle legality is enabled and everything 2015-02-20 03:59:35 +00:00
XCore Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation 2015-02-20 02:15:36 +00:00