llvm-6502/test/CodeGen
2008-08-14 20:04:46 +00:00
..
Alpha
ARM It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool. 2008-08-08 06:56:16 +00:00
CBackend
CellSPU
CPP
Generic Improve support for vector casts in LLVM IR and CodeGen. 2008-08-14 20:04:46 +00:00
IA64
Mips Support added for ctlz intrinsic, test case added. 2008-08-08 06:16:31 +00:00
PowerPC
SPARC
X86 Allow SelectionDAG to create EXTRACT_VECTOR_ELT nodes with 2008-08-13 21:51:37 +00:00