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In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7) using the stored %fp and register windows. However, this does not guarantee that the longjmp will restore the registers, as they were when the setjmp was called. This is because these registers may be clobbered after returning from setjmp, but before calling longjmp. This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190033 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
6.7 KiB
C++
192 lines
6.7 KiB
C++
//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcRegisterInfo.h"
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#include "Sparc.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "SparcGenRegisterInfo.inc"
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using namespace llvm;
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static cl::opt<bool>
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ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
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cl::desc("Reserve application registers (%g2-%g4)"));
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SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
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: SparcGenRegisterInfo(SP::I7), Subtarget(st) {
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}
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const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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return CSR_SaveList;
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}
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const uint32_t*
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SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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return CSR_RegMask;
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}
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const uint32_t*
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SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
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return RTCSR_RegMask;
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}
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// FIXME: G1 reserved for now for large imm generation by frame code.
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Reserved.set(SP::G1);
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// G1-G4 can be used in applications.
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if (ReserveAppRegisters) {
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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}
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// G5 is not reserved in 64 bit mode.
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if (!Subtarget.is64Bit())
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Reserved.set(SP::G5);
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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// Unaliased double registers are not available in non-V9 targets.
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if (!Subtarget.isV9()) {
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for (unsigned n = 0; n != 16; ++n) {
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for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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}
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}
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return Reserved;
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}
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const TargetRegisterClass*
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SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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}
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static void replaceFI(MachineFunction &MF,
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MachineBasicBlock::iterator II,
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MachineInstr &MI,
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DebugLoc dl,
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unsigned FIOperandNum, int Offset,
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unsigned FramePtr)
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{
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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void
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(FIOperandNum + 1).getImm() +
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Subtarget.getStackPointerBias();
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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unsigned FramePtr = SP::I6;
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if (FuncInfo->isLeafProc()) {
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// Use %sp and adjust offset if needed.
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FramePtr = SP::O6;
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int stackSize = MF.getFrameInfo()->getStackSize();
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Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
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}
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if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
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if (MI.getOpcode() == SP::STQFri) {
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned SrcReg = MI.getOperand(2).getReg();
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unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
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unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
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.addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
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replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
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MI.setDesc(TII.get(SP::STDFri));
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MI.getOperand(2).setReg(SrcOddReg);
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Offset += 8;
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} else if (MI.getOpcode() == SP::LDQFri) {
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
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unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
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.addReg(FramePtr).addImm(0);
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replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
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MI.setDesc(TII.get(SP::LDDFri));
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MI.getOperand(0).setReg(DestOddReg);
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Offset += 8;
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}
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}
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replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
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}
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return SP::I6;
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}
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unsigned SparcRegisterInfo::getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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}
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unsigned SparcRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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