llvm-6502/lib/Target/R600
Ahmed Bougacha 7fac1d945f [SelectionDAG] Allow targets to specify legality of extloads' result
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225421 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-08 00:51:32 +00:00
..
AsmParser R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
InstPrinter
MCTargetDesc R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
TargetInfo R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPU.h R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPU.td
AMDGPUAlwaysInlinePass.cpp
AMDGPUAsmPrinter.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
AMDGPUInstructions.td
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
AMDGPUISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
AMDGPUISelLowering.h R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPUTargetMachine.h R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
CaymanInstructions.td
CIInstructions.td
CMakeLists.txt
EvergreenInstructions.td
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600Intrinsics.td
R600ISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
SIFixSGPRCopies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp
SIFoldOperands.cpp R600/SI: Commute instructions to enable more folding opportunities 2015-01-07 22:44:19 +00:00
SIInsertWaits.cpp R600/SI: Insert s_waitcnt before s_barrier instructions. 2015-01-06 19:52:07 +00:00
SIInstrFormats.td
SIInstrInfo.cpp R600/SI: Commute instructions to enable more folding opportunities 2015-01-07 22:44:19 +00:00
SIInstrInfo.h R600/SI: Teach SIFoldOperands to split 64-bit constants when folding 2015-01-07 19:56:17 +00:00
SIInstrInfo.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIInstructions.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIIntrinsics.td
SIISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
SIISelLowering.h R600/SI: Add combine for isinfinite pattern 2015-01-06 23:00:46 +00:00
SILoadStoreOptimizer.cpp
SILowerControlFlow.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SILowerI1Copies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIRegisterInfo.h R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIRegisterInfo.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SISchedule.td
SIShrinkInstructions.cpp
SITypeRewriter.cpp
VIInstrFormats.td
VIInstructions.td R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00