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======================
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LLVM 3.3 Release Notes
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======================
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.. contents::
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:local:
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 3.3. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <http://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
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have questions or comments, the `LLVM Developer's Mailing List
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<http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev>`_ is a good place to send
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them.
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Note that if you are reading this file from a Subversion checkout or the main
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LLVM web page, this document applies to the *next* release, not the current
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one. To see the release notes for a specific release, please see the `releases
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page <http://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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* The CellSPU port has been removed. It can still be found in older versions.
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* The IR-level extended linker APIs (for example, to link bitcode files out of
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archives) have been removed. Any existing clients of these features should
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move to using a linker with integrated LTO support.
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* LLVM and Clang's documentation has been migrated to the `Sphinx
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<http://sphinx-doc.org/>`_ documentation generation system which uses
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easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
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information.
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* TargetTransformInfo (TTI) is a new interface that can be used by IR-level
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passes to obtain target-specific information, such as the costs of
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instructions. Only "Lowering" passes such as LSR and the vectorizer are
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allowed to use the TTI infrastructure.
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* We've improved the X86 and ARM cost model.
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* The Attributes classes have been completely rewritten and expanded. They now
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support not only enumerated attributes and alignments, but "string"
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attributes, which are useful for passing information to code generation. See
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:doc:`HowToUseAttributes` for more details.
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* TableGen's syntax for instruction selection patterns has been simplified.
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Instead of specifying types indirectly with register classes, you should now
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specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
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examples of the new syntax. The old syntax using register classes still
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works, but it will be removed in a future LLVM release.
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* MCJIT now supports exception handling. Support for it in the old jit will be
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removed in the 3.4 release.
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* Command line options can now be grouped into categories which are shown in
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the output of ``-help``. See :ref:`grouping options into categories`.
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* The appearance of command line options in ``-help`` that are inherited by
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linking with libraries that use the LLVM Command line support library can now
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be modified at runtime. See :ref:`cl::getRegisteredOptions`.
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AArch64 target
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--------------
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We've added support for AArch64, ARM's 64-bit architecture. Development is still
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in fairly early stages, but we expect successful compilation when:
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- compiling standard compliant C99 and C++03 with Clang;
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- using Linux as a target platform;
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- where code + static data doesn't exceed 4GB in size (heap allocated data has
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no limitation).
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Some additional functionality is also implemented, notably DWARF debugging,
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GNU-style thread local storage and inline assembly.
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Hexagon Target
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--------------
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Removed support for legacy hexagonv2 and hexagonv3 processor architectures which
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are no longer in use. Currently supported architectures are hexagonv4 and
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hexagonv5.
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Mips target
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--------------
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New features and improvements:
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- Clang driver
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- Support for Sourcery CodeBench Mips toolchain directories tree.
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- Support for new command line options including:
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- -mxgot/-mno-xgot
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- -EL / -EB
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- -mmicromips / -mno-micromips
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- -msingle-float / -mdouble-float
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- -mabi=32 (o32 abi) and -mabi=64 (n64 abi)
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- Previously, options such as -mips16, -mmicromips, -mdsp and -mdspr2 were
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not passed to the assembler. This issue has been fixed.
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- A number of changes have been made to improve the quality of DSP-ASE code
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generation.
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- Multiply and multiply-accumulate instructions can now use all four
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accumulators.
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- Instruction selection patterns have been added so that DSP instructions
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are emitted without having to use builtins.
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- Delay slot filler pass can now search successor blocks for instructions to
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fill delay slots (use option -disable-mips-df-succbb-search=false).
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PowerPC Target
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--------------
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New features and improvements:
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- PowerPC now supports an assembly parser.
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- Support added for thread-local storage. 64-bit ELF subtarget only.
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- Support added for medium and large code model (-mcmodel=medium,large).
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Medium code model is now the default. 64-bit ELF subtarget only.
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- Improved register allocation (fewer reserved registers).
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- 64-bit atomic load and store are now supported.
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- Improved code generation for unaligned memory accesses of scalar types.
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- Improved performance of floating-point divide and square root
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with -ffast-math.
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- Support for predicated returns.
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- Improved code generation for comparisons.
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- Support added for inline setjmp and longjmp.
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- Support added for many instructions introduced in PowerISA 2.04, 2.05,
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and 2.06.
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- Improved spill code for vector registers.
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- Support added for -mno-altivec.
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- ABI compatibility fixes for complex parameters, 128-bit integer parameters,
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and varargs functions. 64-bit ELF subtarget only.
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Loop Vectorizer
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---------------
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We've continued the work on the loop vectorizer. The loop vectorizer now
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has the following features:
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- Loops with unknown trip counts.
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- Runtime checks of pointers.
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- Reductions, Inductions.
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- Min/Max reductions of integers.
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- If Conversion.
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- Pointer induction variables.
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- Reverse iterators.
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- Vectorization of mixed types.
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- Vectorization of function calls.
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- Partial unrolling during vectorization.
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The loop vectorizer is now enabled by default for -O3.
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SLP Vectorizer
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--------------
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LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
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default but can be enabled using the clang flag ``-fslp-vectorize``. The
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BB-vectorizer can also be enabled using the command line flag
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``-fslp-vectorize-aggressive``.
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R600 Backend
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------------
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The R600 backend was added in this release, it supports AMD GPUs (HD2XXX -
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HD7XXX). This backend is used in AMD's Open Source graphics / compute drivers
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which are developed as part of the `Mesa3D <http://www.mesa3d.org>`_ project.
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SystemZ/s390x Backend
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---------------------
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LLVM and clang now support IBM's z/Architecture. At present this support
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is restricted to GNU/Linux (GNU triplet s390x-linux-gnu) and requires
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z10 or greater.
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Sub-project Status Update
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=========================
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In addition to the core LLVM 3.3 distribution of production-quality compiler
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infrastructure, the LLVM project includes sub-projects that use the LLVM core
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and share the same distribution license. This section provides updates on these
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sub-projects.
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DragonEgg: GCC front-ends, LLVM back-end
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----------------------------------------
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`DragonEgg <http://dragonegg.llvm.org/>`_ is a
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`GCC plugin <http://gcc.gnu.org/wiki/plugins>`_ that replaces GCC's optimizers
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and code generators with LLVM's. It works with gcc-4.5, 4.6, 4.7 and 4.8, can
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target the x86-32/x86-64 and ARM processor families, and has been successfully
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used on the Darwin, FreeBSD, KFreeBSD, Linux and OpenBSD platforms. It fully
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supports Ada, C, C++ and Fortran. It has partial support for Go, Java, Obj-C
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and Obj-C++. Note that gcc-4.6 is the best supported version, and that Ada in
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particular doesn't work well with gcc-4.7 and newer.
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The `3.3 release <http://llvm.org/apt/>`_ has the following notable changes.
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- supports gcc-4.8 (requires gcc-4.8.1 or newer)
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- object files can be written directly using LLVM's integrated assembler
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- produces saner debug info
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- bitfields can now contain arbitrary scalar types (useful for Ada)
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LLDB: Low Level Debugger
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------------------------
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`LLDB <http://lldb.llvm.org/>`_ is a ground-up implementation of a command-line
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debugger, as well as a debugger API that can be used from scripts and other
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applications. LLDB uses the following components of the LLVM core distribution
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to support the latest language features and target support:
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- the Clang parser for high-quality parsing of C, C++ and Objective C
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- the LLVM disassembler
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- the LLVM JIT compiler (MCJIT) for expression evaluation
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The `3.3 release <http://lldb.llvm.org/download.html>`_ has the following notable changes.
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Features now supported on Linux:
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- Debugging multi-threaded programs
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- Support for watchpoints
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- Process list, attach and fork
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- `vim integration <http://llvm.org/svn/llvm-project/lldb/branches/release_33/utils/vim-lldb/README>`_ for LLDB
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Portability:
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- Builds with cmake, ninja, auto-tools, clang 3.3 and gcc 4.6
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Linux Improvements:
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- Improved register support including vector registers
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- Basic debugging of i386 programs
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- Bug fixes for expression evaluation
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External Open Source Projects Using LLVM 3.3
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============================================
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An exciting aspect of LLVM is that it is used as an enabling technology for a
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lot of other language and tools projects. This section lists some of the
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projects that have already been updated to work with LLVM 3.3.
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Portable Computing Language (pocl)
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----------------------------------
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In addition to producing an easily portable open source OpenCL implementation,
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another major goal of `pocl <http://pocl.sourceforge.net/>`_ is improving
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performance portability of OpenCL programs with compiler optimizations, reducing
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the need for target-dependent manual optimizations. An important part of pocl is
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a set of LLVM passes used to statically parallelize multiple work-items with the
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kernel compiler, even in the presence of work-group barriers. This enables
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static parallelization of the fine-grained static concurrency in the work groups
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in multiple ways.
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TTA-based Co-design Environment (TCE)
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-------------------------------------
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`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new processors based
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on the Transport triggered architecture (TTA). The toolset provides a complete
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co-design flow from C/C++ programs down to synthesizable VHDL/Verilog and
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parallel program binaries. Processor customization points include the register
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files, function units, supported operations, and the interconnection network.
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TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
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optimizations and also for parts of code generation. It generates new LLVM-based
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code generators "on the fly" for the designed TTA processors and loads them in
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to the compiler backend as runtime libraries to avoid per-target recompilation
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of larger parts of the compiler chain.
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Just-in-time Adaptive Decoder Engine (Jade)
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-------------------------------------------
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`Jade <https://github.com/orcc/jade>`_ (Just-in-time Adaptive Decoder Engine) is
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a generic video decoder engine using LLVM for just-in-time compilation of video
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decoder configurations. Those configurations are designed by MPEG Reconfigurable
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Video Coding (RVC) committee. MPEG RVC standard is built on a stream-based
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dataflow representation of decoders. It is composed of a standard library of
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coding tools written in RVC-CAL language and a dataflow configuration --- block
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diagram --- of a decoder.
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Jade project is hosted as part of the Open RVC-CAL Compiler (`Orcc
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<http://orcc.sf.net>`_) and requires it to translate the RVC-CAL standard
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library of video coding tools into an LLVM assembly code.
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LDC - the LLVM-based D compiler
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-------------------------------
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`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
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pragmatically combines efficiency, control, and modeling power, with safety and
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programmer productivity. D supports powerful concepts like Compile-Time Function
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Execution (CTFE) and Template Meta-Programming, provides an innovative approach
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to concurrency and offers many classical paradigms.
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`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
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combined with LLVM as backend to produce efficient native code. LDC targets
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x86/x86_64 systems like Linux, OS X and Windows and also Linux/PPC64. Ports to
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other architectures like ARM are underway.
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<http://llvm.org/>`_, in particular in the `documentation
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<http://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Subversion version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `mailing lists <http://llvm.org/docs/#maillist>`_.
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