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04402a6c13
AVX is available, and generally tidy up things surrounding UNPCK formation. Originally, I was thinking that the only advantage of PSHUFD over UNPCK instruction variants was its free copy, and otherwise we should use the shorter encoding UNPCK instructions. This isn't right though, there is a larger advantage of being able to fold a load into the operand of a PSHUFD. For UNPCK, the operand *must* be in a register so it can be the second input. This removes the UNPCK formation in the target-specific DAG combine for v4i32 shuffles. It also lifts the v8 and v16 cases out of the AVX-specific check as they are potentially replacing multiple instructions with a single instruction and so should always be valuable. The floating point checks are simplified accordingly. This also adjusts the formation of PSHUFD instructions to attempt to match the shuffle mask to one which would fit an UNPCK instruction variant. This was originally motivated to allow it to match the UNPCK instructions in the combiner, but clearly won't now. Eventually, we should add a MachineCombiner pass that can form UNPCK instructions post-RA when the operand is known to be in a register and thus there is no loss. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217755 91177308-0d34-0410-b5e6-96231b3b80d8
383 lines
16 KiB
LLVM
383 lines
16 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=AVX1
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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define <4 x i64> @shuffle_v4i64_0001(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0001
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; AVX1: # BB#0:
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0020(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0020
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpunpcklqdq {{.*}} # xmm1 = xmm1[0],xmm0[0]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0112(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0112
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1],xmm1[0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 1, i32 2>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0300(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0300
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_1000(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_1000
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; AVX1: # BB#0:
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm0[2,3,0,1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_2200(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_2200
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_3330(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_3330
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0]
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,2,3]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_3210(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_3210
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,0,1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[2,3,0,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i64> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0001(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0001
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; AVX1: # BB#0:
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0020(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0020
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0],xmm0[0]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0300(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0300
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1000(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1000
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; AVX1: # BB#0:
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm0[1,0]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_2200(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_2200
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm1 = xmm1[0,0]
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; AVX1-NEXT: vunpcklpd {{.*}} # xmm0 = xmm0[0,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_3330(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_3330
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm1[1],xmm0[0]
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; AVX1-NEXT: vmovhlps {{.*}} # xmm1 = xmm1[1,1]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_3210(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_3210
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufpd {{.*}} # xmm1 = xmm1[1,0]
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; AVX1-NEXT: vshufpd {{.*}} # xmm0 = xmm0[1,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0023(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0023
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[0,0,2,3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0022(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0022
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[0,0,2,2]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1032(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1032
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[1,0,3,2]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1133(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1133
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[1,1,3,3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1023(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1023
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[1,0,2,3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 0, i32 2, i32 3>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1022(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1022
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[1,0,2,2]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 0, i32 2, i32 2>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0423(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0423
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm1 = ymm1[{{[0-9]}},0,{{[0-9],[0-9]}}]
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; AVX1-NEXT: vblendpd {{.*}} # ymm0 = ymm0[0],ymm1[1],ymm0[2,3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0462(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0462
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; AVX1: # BB#0:
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; AVX1-NEXT: vpermilpd {{.*}} # ymm1 = ymm1[{{[0-9]}},0,2,{{[0-9]}}]
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; AVX1-NEXT: vpermilpd {{.*}} # ymm0 = ymm0[0,{{[0-9],[0-9]}},2]
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; AVX1-NEXT: vblendpd {{.*}} # ymm0 = ymm0[0],ymm1[1,2],ymm0[3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 6, i32 2>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_0426(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_0426
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; AVX1: # BB#0:
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; AVX1-NEXT: vunpcklpd {{.*}} # ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_1537(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_1537
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; AVX1: # BB#0:
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; AVX1-NEXT: vunpckhpd {{.*}} # ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_4062(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_4062
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; AVX1: # BB#0:
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; AVX1-NEXT: vunpcklpd {{.*}} # ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 4, i32 0, i32 6, i32 2>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_5173(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_5173
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; AVX1: # BB#0:
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; AVX1-NEXT: vunpckhpd {{.*}} # ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 5, i32 1, i32 7, i32 3>
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ret <4 x double> %shuffle
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}
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define <4 x double> @shuffle_v4f64_5163(<4 x double> %a, <4 x double> %b) {
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; AVX1-LABEL: @shuffle_v4f64_5163
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; AVX1: # BB#0:
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; AVX1-NEXT: vshufpd {{.*}} # ymm0 = ymm1[1],ymm0[1],ymm1[2],ymm0[3]
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 5, i32 1, i32 6, i32 3>
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ret <4 x double> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0124(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0124
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm2[0],xmm1[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0142(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0142
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm2[0,1,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm1 = xmm1[0],xmm2[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0412(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0412
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_4012(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_4012
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vshufpd {{.*}} # xmm2 = xmm0[1],xmm2[0]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 2>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0145(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0145
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; AVX1: # BB#0:
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_0451(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_0451
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; AVX1: # BB#0:
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; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm1[2,3,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm2 = xmm2[0],xmm0[1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[0,1,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 1>
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ret <4 x i64> %shuffle
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}
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define <4 x i64> @shuffle_v4i64_4501(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_4501
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; AVX1: # BB#0:
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
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ret <4 x i64> %shuffle
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|
}
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define <4 x i64> @shuffle_v4i64_4015(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-LABEL: @shuffle_v4i64_4015
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; AVX1: # BB#0:
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; AVX1-NEXT: vpshufd {{.*}} # xmm2 = xmm0[2,3,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm2 = xmm2[0],xmm1[1]
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; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[0,1,0,1]
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; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm1[0],xmm0[1]
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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%shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 0, i32 1, i32 5>
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|
ret <4 x i64> %shuffle
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|
}
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define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
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|
; AVX1-LABEL: @stress_test1
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|
; AVX1: # BB#0:
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|
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0
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|
; AVX1-NEXT: vpshufd {{.*}} # xmm0 = xmm0[2,3,2,3]
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|
; AVX1-NEXT: vblendpd {{.*}} # xmm0 = xmm0[0],xmm1[1]
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|
; AVX1-NEXT: vpshufd {{.*}} # xmm1 = xmm1[2,3,0,1]
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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|
; AVX1-NEXT: retq
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|
%c = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 1, i32 1, i32 0>
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|
%d = shufflevector <4 x i64> %c, <4 x i64> undef, <4 x i32> <i32 3, i32 undef, i32 2, i32 undef>
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|
%e = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 3, i32 1, i32 undef>
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|
%f = shufflevector <4 x i64> %d, <4 x i64> %e, <4 x i32> <i32 5, i32 1, i32 1, i32 0>
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|
|
|
ret <4 x i64> %f
|
|
}
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