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https://github.com/c64scene-ar/llvm-6502.git
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861986401e
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
702 lines
26 KiB
TableGen
702 lines
26 KiB
TableGen
//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Thumb specific DAG Nodes.
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//
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def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
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}]>;
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def imm_comp_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
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}]>;
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/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
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def imm0_7 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 8;
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}]>;
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def imm0_7_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getZExtValue() < 8;
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}], imm_neg_XFORM>;
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def imm0_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 256;
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}]>;
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def imm0_255_comp : PatLeaf<(i32 imm), [{
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return ~((uint32_t)N->getZExtValue()) < 256;
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}]>;
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def imm8_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
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}]>;
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def imm8_255_neg : PatLeaf<(i32 imm), [{
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unsigned Val = -N->getZExtValue();
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return Val >= 8 && Val < 256;
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}], imm_neg_XFORM>;
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// Break imm's up into two pieces: an immediate + a left shift.
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// This uses thumb_immshifted to match and thumb_immshifted_val and
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// thumb_immshifted_shamt to get the val/shift pieces.
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def thumb_immshifted : PatLeaf<(imm), [{
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return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
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}]>;
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def thumb_immshifted_val : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def thumb_immshifted_shamt : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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// Define Thumb specific addressing modes.
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// t_addrmode_rr := reg + reg
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//
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def t_addrmode_rr : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
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let PrintMethod = "printThumbAddrModeRROperand";
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let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
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}
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// t_addrmode_s4 := reg + reg
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// reg + imm5 * 4
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//
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def t_addrmode_s4 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
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let PrintMethod = "printThumbAddrModeS4Operand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
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}
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// t_addrmode_s2 := reg + reg
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// reg + imm5 * 2
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//
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def t_addrmode_s2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
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let PrintMethod = "printThumbAddrModeS2Operand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
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}
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// t_addrmode_s1 := reg + reg
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// reg + imm5
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//
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def t_addrmode_s1 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
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let PrintMethod = "printThumbAddrModeS1Operand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
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}
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// t_addrmode_sp := sp + imm8 * 4
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//
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def t_addrmode_sp : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
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let PrintMethod = "printThumbAddrModeSPOperand";
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//
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let Defs = [SP], Uses = [SP] in {
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def tADJCALLSTACKUP :
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PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
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"@ tADJCALLSTACKUP $amt1",
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[(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
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def tADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
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"@ tADJCALLSTACKDOWN $amt",
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[(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
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}
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// For both thumb1 and thumb2.
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let isNotDuplicable = 1 in
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALU,
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"$cp:\n\tadd $dst, pc",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
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// PC relative add.
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALU,
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"add $dst, pc, $rhs * 4", []>;
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// ADD rd, sp, #imm8
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALU,
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"add $dst, $sp, $rhs * 4 @ addrspi", []>;
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// ADD sp, sp, #imm7
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def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
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"add $dst, $rhs * 4", []>;
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// SUB sp, sp, #imm7
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def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
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"sub $dst, $rhs * 4", []>;
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// ADD rm, sp, rm
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def tADDrSPr : TI<(outs GPR:$dst), (ins GPR:$sp, GPR:$rhs), IIC_iALU,
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"add $dst, $sp, $rhs", []>;
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// ADD sp, rm
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def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
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"add $dst, $rhs", []>;
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// Pseudo instruction that will expand into a tSUBspi + a copy.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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NoItinerary, "@ sub $dst, $rhs * 4", []>;
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def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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NoItinerary, "@ add $dst, $rhs", []>;
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let Defs = [CPSR] in
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def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
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NoItinerary, "@ and $dst, $rhs", []>;
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} // usesCustomDAGSchedInserter
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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let isReturn = 1, isTerminator = 1 in {
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def tBX_RET : TI<(outs), (ins), IIC_Br, "bx lr", [(ARMretflag)]>;
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx $target", []>;
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1 in
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def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
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"pop $dst1", []>;
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R12, LR,
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D0, D1, D2, D3, D4, D5, D6, D7,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
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// Also used for Thumb2
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def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"bl ${func:call}",
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[(ARMtcall tglobaladdr:$func)]>,
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Requires<[IsThumb, IsNotDarwin]>;
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// ARMv5T and above, also used for Thumb2
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def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"blx ${func:call}",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsThumb, HasV5T, IsNotDarwin]>;
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// Also used for Thumb2
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def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
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"blx $func",
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[(ARMtcall GPR:$func)]>,
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Requires<[IsThumb, HasV5T, IsNotDarwin]>;
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// ARMv4T
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def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb1Only, IsNotDarwin]>;
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}
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// On Darwin R9 is call-clobbered.
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let isCall = 1,
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Defs = [R0, R1, R2, R3, R9, R12, LR,
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D0, D1, D2, D3, D4, D5, D6, D7,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
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// Also used for Thumb2
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def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"bl ${func:call}",
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[(ARMtcall tglobaladdr:$func)]>,
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Requires<[IsThumb, IsDarwin]>;
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// ARMv5T and above, also used for Thumb2
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def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
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"blx ${func:call}",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsThumb, HasV5T, IsDarwin]>;
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// Also used for Thumb2
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def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
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"blx $func",
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[(ARMtcall GPR:$func)]>,
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Requires<[IsThumb, HasV5T, IsDarwin]>;
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// ARMv4T
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def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov lr, pc\n\tbx $func",
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[(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsThumb1Only, IsDarwin]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1 in {
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let isPredicable = 1 in
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def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
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"b $target", [(br bb:$target)]>;
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// Far jump
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def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
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"bl $target\t@ far jump",[]>;
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def tBR_JTr : T1JTI<(outs),
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(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
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IIC_Br, "mov pc, $target\n\t.align\t2\n$jt",
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[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
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}
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}
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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let isBranch = 1, isTerminator = 1 in
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def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
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"b$cc $target",
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[/*(ARMbrcond bb:$target, imm:$cc)*/]>;
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//===----------------------------------------------------------------------===//
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// Load Store Instructions.
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//
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let canFoldAsLoad = 1 in
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def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad,
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"ldr", " $dst, $addr",
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[(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
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def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad,
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"ldrb", " $dst, $addr",
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[(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
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def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad,
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"ldrh", " $dst, $addr",
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[(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
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let AddedComplexity = 10 in
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def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad,
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"ldrsb", " $dst, $addr",
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[(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
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let AddedComplexity = 10 in
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def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad,
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"ldrsh", " $dst, $addr",
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[(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
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let canFoldAsLoad = 1 in
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def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad,
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"ldr", " $dst, $addr",
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[(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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let canFoldAsLoad = 1, mayLoad = 1 in
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def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad,
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"ldr", " $dst, $addr", []>;
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// Load tconstpool
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let canFoldAsLoad = 1 in
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def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad,
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"ldr", " $dst, $addr",
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[(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
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def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad,
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"ldr", " $dst, $addr", []>;
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def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore,
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"str", " $src, $addr",
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[(store tGPR:$src, t_addrmode_s4:$addr)]>;
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def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore,
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"strb", " $src, $addr",
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[(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
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def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore,
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"strh", " $src, $addr",
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[(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
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def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
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"str", " $src, $addr",
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[(store tGPR:$src, t_addrmode_sp:$addr)]>;
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let mayStore = 1 in {
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// Special instruction for spill. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
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"str", " $src, $addr", []>;
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}
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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// TODO: A7-44: LDMIA - load multiple
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// TODO: Allow these to be predicated
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let mayLoad = 1 in
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def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
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"pop $dst1", []>;
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let mayStore = 1 in
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def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops), IIC_Br,
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"push $src1", []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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// Add with carry register
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let isCommutable = 1, Uses = [CPSR] in
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def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
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"adc", " $dst, $rhs",
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[(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
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// Add immediate
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def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
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"add", " $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
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def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
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"add", " $dst, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
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// Add register
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let isCommutable = 1 in
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def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
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"add", " $dst, $lhs, $rhs",
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[(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
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let neverHasSideEffects = 1 in
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def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
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"add", " $dst, $rhs @ addhirr", []>;
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// And register
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let isCommutable = 1 in
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def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"and", " $dst, $rhs",
|
|
[(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// ASR immediate
|
|
def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"asr", " $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
|
|
|
|
// ASR register
|
|
def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"asr", " $dst, $rhs",
|
|
[(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// BIC register
|
|
def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"bic", " $dst, $rhs",
|
|
[(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
|
|
|
|
// CMN register
|
|
let Defs = [CPSR] in {
|
|
def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"cmn", " $lhs, $rhs",
|
|
[(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
|
|
def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"cmn", " $lhs, $rhs",
|
|
[(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
|
|
}
|
|
|
|
// CMP immediate
|
|
let Defs = [CPSR] in {
|
|
def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"cmp", " $lhs, $rhs",
|
|
[(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
|
|
def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"cmp", " $lhs, $rhs",
|
|
[(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
|
|
|
|
}
|
|
|
|
// CMP register
|
|
let Defs = [CPSR] in {
|
|
def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"cmp", " $lhs, $rhs",
|
|
[(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
|
|
def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"cmp", " $lhs, $rhs",
|
|
[(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
|
|
|
|
// TODO: Make use of the followings cmp hi regs
|
|
def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
|
|
"cmp", " $lhs, $rhs", []>;
|
|
def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
|
|
"cmp", " $lhs, $rhs", []>;
|
|
}
|
|
|
|
|
|
// XOR register
|
|
let isCommutable = 1 in
|
|
def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"eor", " $dst, $rhs",
|
|
[(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// LSL immediate
|
|
def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"lsl", " $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
|
|
|
|
// LSL register
|
|
def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"lsl", " $dst, $rhs",
|
|
[(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// LSR immediate
|
|
def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"lsr", " $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
|
|
|
|
// LSR register
|
|
def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"lsr", " $dst, $rhs",
|
|
[(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// move register
|
|
def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iALU,
|
|
"mov", " $dst, $src",
|
|
[(set tGPR:$dst, imm0_255:$src)]>;
|
|
|
|
// TODO: A7-73: MOV(2) - mov setting flag.
|
|
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
// FIXME: Make this predicable.
|
|
def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"mov $dst, $src", []>;
|
|
let Defs = [CPSR] in
|
|
def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"movs $dst, $src", []>;
|
|
|
|
// FIXME: Make these predicable.
|
|
def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iALU,
|
|
"mov $dst, $src\t@ hir2lor", []>;
|
|
def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"mov $dst, $src\t@ lor2hir", []>;
|
|
def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
|
|
"mov $dst, $src\t@ hir2hir", []>;
|
|
} // neverHasSideEffects
|
|
|
|
// multiply register
|
|
let isCommutable = 1 in
|
|
def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"mul", " $dst, $rhs",
|
|
[(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// move inverse register
|
|
def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"mvn", " $dst, $src",
|
|
[(set tGPR:$dst, (not tGPR:$src))]>;
|
|
|
|
// bitwise or register
|
|
let isCommutable = 1 in
|
|
def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"orr", " $dst, $rhs",
|
|
[(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// swaps
|
|
def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"rev", " $dst, $src",
|
|
[(set tGPR:$dst, (bswap tGPR:$src))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"rev16", " $dst, $src",
|
|
[(set tGPR:$dst,
|
|
(or (and (srl tGPR:$src, (i32 8)), 0xFF),
|
|
(or (and (shl tGPR:$src, (i32 8)), 0xFF00),
|
|
(or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
|
|
(and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"revsh", " $dst, $src",
|
|
[(set tGPR:$dst,
|
|
(sext_inreg
|
|
(or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
|
|
(shl tGPR:$src, (i32 8))), i16))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
// rotate right register
|
|
def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"ror", " $dst, $rhs",
|
|
[(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// negate register
|
|
def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"rsb", " $dst, $src, #0",
|
|
[(set tGPR:$dst, (ineg tGPR:$src))]>;
|
|
|
|
// Subtract with carry register
|
|
let Uses = [CPSR] in
|
|
def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"sbc", " $dst, $rhs",
|
|
[(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// Subtract immediate
|
|
def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"sub", " $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
|
|
|
|
def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
|
|
"sub", " $dst, $rhs",
|
|
[(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
|
|
|
|
// subtract register
|
|
def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"sub", " $dst, $lhs, $rhs",
|
|
[(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
|
|
|
|
// TODO: A7-96: STMIA - store multiple.
|
|
|
|
// sign-extend byte
|
|
def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"sxtb", " $dst, $src",
|
|
[(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
// sign-extend short
|
|
def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"sxth", " $dst, $src",
|
|
[(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
// test
|
|
let isCommutable = 1, Defs = [CPSR] in
|
|
def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
|
|
"tst", " $lhs, $rhs",
|
|
[(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
|
|
|
|
// zero-extend byte
|
|
def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"uxtb", " $dst, $src",
|
|
[(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
// zero-extend short
|
|
def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
|
|
"uxth", " $dst, $src",
|
|
[(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
|
|
Requires<[IsThumb1Only, HasV6]>;
|
|
|
|
|
|
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
|
|
// Expanded by the scheduler into a branch sequence.
|
|
// FIXME: Add actual movcc in IT blocks for Thumb2.
|
|
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
|
|
def tMOVCCr :
|
|
PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), IIC_iALU,
|
|
"@ tMOVCCr $cc",
|
|
[/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
|
|
|
|
// tLEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
|
|
"adr $dst, #$label", []>;
|
|
|
|
def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), IIC_iALU,
|
|
"adr $dst, #${label}_${id:no_hash}", []>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// TLS Instructions
|
|
//
|
|
|
|
// __aeabi_read_tp preserves the registers r1-r3.
|
|
let isCall = 1,
|
|
Defs = [R0, LR] in {
|
|
def tTPsoft : TIx2<(outs), (ins), IIC_Br,
|
|
"bl __aeabi_read_tp",
|
|
[(set R0, ARMthread_pointer)]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// Add with carry
|
|
def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
|
|
(tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
|
|
def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
|
|
(tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
|
|
def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
|
|
(tADDrr tGPR:$lhs, tGPR:$rhs)>;
|
|
|
|
// Subtract with carry
|
|
def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
|
|
(tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
|
|
def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
|
|
(tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
|
|
def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
|
|
(tSUBrr tGPR:$lhs, tGPR:$rhs)>;
|
|
|
|
// ConstantPool, GlobalAddress
|
|
def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
|
|
def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
|
|
|
|
// JumpTable
|
|
def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(tLEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// Direct calls
|
|
def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
|
|
Requires<[IsThumb, IsNotDarwin]>;
|
|
def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
|
|
Requires<[IsThumb, IsDarwin]>;
|
|
|
|
def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
|
|
Requires<[IsThumb, HasV5T, IsNotDarwin]>;
|
|
def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
|
|
Requires<[IsThumb, HasV5T, IsDarwin]>;
|
|
|
|
// Indirect calls to ARM routines
|
|
def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
|
|
Requires<[IsThumb, HasV5T, IsNotDarwin]>;
|
|
def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
|
|
Requires<[IsThumb, HasV5T, IsDarwin]>;
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
|
|
(tLDRB t_addrmode_s1:$addr)>;
|
|
|
|
// extload -> zextload
|
|
def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
|
|
|
|
// If it's possible to use [r,r] address mode for sextload, select to
|
|
// ldr{b|h} + sxt{b|h} instead.
|
|
def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
|
|
(tSXTB (tLDRB t_addrmode_s1:$addr))>;
|
|
def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
|
|
(tSXTH (tLDRH t_addrmode_s2:$addr))>;
|
|
|
|
|
|
// Large immediate handling.
|
|
|
|
// Two piece imms.
|
|
def : T1Pat<(i32 thumb_immshifted:$src),
|
|
(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
|
|
(thumb_immshifted_shamt imm:$src))>;
|
|
|
|
def : T1Pat<(i32 imm0_255_comp:$src),
|
|
(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
|