mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-04 07:29:20 +00:00
fce288fc91
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
4.8 KiB
LLVM
110 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v8qi3 = type { <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v8qi4 = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vtbl1:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__builtin_neon_v8qi2* %B) nounwind {
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;CHECK: vtbl2:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi2* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 1
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%tmp5 = call <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4)
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ret <8 x i8> %tmp5
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}
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define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__builtin_neon_v8qi3* %B) nounwind {
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;CHECK: vtbl3:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi3* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 2
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__builtin_neon_v8qi4* %B) nounwind {
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;CHECK: vtbl4:
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;CHECK: vtbl.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi4* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 2
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%tmp6 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 3
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx1:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = load <8 x i8>* %C
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%tmp4 = call <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3)
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ret <8 x i8> %tmp4
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}
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define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__builtin_neon_v8qi2* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx2:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi2* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp2, 1
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%tmp5 = load <8 x i8>* %C
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%tmp6 = call <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5)
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ret <8 x i8> %tmp6
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}
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define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__builtin_neon_v8qi3* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx3:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi3* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi3 %tmp2, 2
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%tmp6 = load <8 x i8>* %C
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%tmp7 = call <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6)
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ret <8 x i8> %tmp7
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}
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define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__builtin_neon_v8qi4* %B, <8 x i8>* %C) nounwind {
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;CHECK: vtbx4:
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;CHECK: vtbx.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load %struct.__builtin_neon_v8qi4* %B
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%tmp3 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 0
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 1
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 2
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%tmp6 = extractvalue %struct.__builtin_neon_v8qi4 %tmp2, 3
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%tmp7 = load <8 x i8>* %C
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%tmp8 = call <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8> %tmp1, <8 x i8> %tmp3, <8 x i8> %tmp4, <8 x i8> %tmp5, <8 x i8> %tmp6, <8 x i8> %tmp7)
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ret <8 x i8> %tmp8
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}
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declare <8 x i8> @llvm.arm.neon.vtbl1(<8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl2(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbl4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx1(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx2(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx3(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone
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