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https://github.com/c64scene-ar/llvm-6502.git
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14b32e1941
possible before resorting to pextrw and pinsrw. - Better codegen for v4i32 shuffles masquerading as v8i16 or v16i8 shuffles. - Improves (i16 extract_vector_element 0) codegen by recognizing (i32 extract_vector_element 0) does not require a pextrw. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44836 91177308-0d34-0410-b5e6-96231b3b80d8
29 lines
1.2 KiB
LLVM
29 lines
1.2 KiB
LLVM
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep punpck
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pextrw | count 4
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pinsrw | count 6
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshuflw | count 3
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufhw | count 2
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define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
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ret <8 x i16> %tmp3
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}
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define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
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ret <8 x i16> %tmp
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}
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define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
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ret <8 x i16> %tmp
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}
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define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
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ret <8 x i16> %tmp
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}
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