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This restores my karma after I added TRI::getSubClassWithSubReg(). Register constraints are applied 'backwards'. Starting from the register class required by an instruction operand, the correct question is: 'How can I constrain the super-register register class so all its sub-registers satisfy the instruction constraint?' The getMatchingSuperRegClass() hook answers that. We never need to go 'forwards': Starting from a super-register register class, what register class are the sub-registers in? The getSubRegisterRegClass() hook did that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
718 lines
29 KiB
C++
718 lines
29 KiB
C++
//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETREGISTERINFO_H
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#define LLVM_TARGET_TARGETREGISTERINFO_H
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/ArrayRef.h"
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#include <cassert>
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#include <functional>
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namespace llvm {
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class BitVector;
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class MachineFunction;
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class RegScavenger;
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template<class T> class SmallVectorImpl;
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class raw_ostream;
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class TargetRegisterClass {
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public:
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typedef const unsigned* iterator;
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typedef const unsigned* const_iterator;
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typedef const EVT* vt_iterator;
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typedef const TargetRegisterClass* const * sc_iterator;
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private:
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const MCRegisterClass *MC;
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const vt_iterator VTs;
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const unsigned *SubClassMask;
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const sc_iterator SuperClasses;
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const sc_iterator SuperRegClasses;
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public:
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TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
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const unsigned *subcm,
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const TargetRegisterClass * const *supcs,
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const TargetRegisterClass * const *superregcs)
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: MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
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SuperRegClasses(superregcs) {}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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/// getID() - Return the register class ID number.
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///
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unsigned getID() const { return MC->getID(); }
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/// getName() - Return the register class name for debugging.
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///
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const char *getName() const { return MC->getName(); }
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/// begin/end - Return all of the registers in this class.
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///
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iterator begin() const { return MC->begin(); }
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iterator end() const { return MC->end(); }
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/// getNumRegs - Return the number of registers in this class.
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///
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unsigned getNumRegs() const { return MC->getNumRegs(); }
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/// getRegister - Return the specified register in the class.
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///
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unsigned getRegister(unsigned i) const {
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return MC->getRegister(i);
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}
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/// contains - Return true if the specified register is included in this
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/// register class. This does not include virtual registers.
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bool contains(unsigned Reg) const {
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return MC->contains(Reg);
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}
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/// contains - Return true if both registers are in this class.
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bool contains(unsigned Reg1, unsigned Reg2) const {
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return MC->contains(Reg1, Reg2);
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return MC->getSize(); }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return MC->getAlignment(); }
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/// getCopyCost - Return the cost of copying a value between two registers in
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/// this class. A negative number means the register class is very expensive
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/// to copy e.g. status flag register classes.
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int getCopyCost() const { return MC->getCopyCost(); }
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/// isAllocatable - Return true if this register class may be used to create
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/// virtual registers.
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bool isAllocatable() const { return MC->isAllocatable(); }
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/// hasType - return true if this TargetRegisterClass has the ValueType vt.
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///
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bool hasType(EVT vt) const {
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for(int i = 0; VTs[i] != MVT::Other; ++i)
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if (VTs[i] == vt)
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return true;
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return false;
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}
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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vt_iterator vt_begin() const {
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return VTs;
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}
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vt_iterator vt_end() const {
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vt_iterator I = VTs;
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while (*I != MVT::Other) ++I;
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return I;
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}
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/// superregclasses_begin / superregclasses_end - Loop over all of
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/// the superreg register classes of this register class.
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sc_iterator superregclasses_begin() const {
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return SuperRegClasses;
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}
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sc_iterator superregclasses_end() const {
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sc_iterator I = SuperRegClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// hasSubClass - return true if the specified TargetRegisterClass
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/// is a proper sub-class of this TargetRegisterClass.
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bool hasSubClass(const TargetRegisterClass *RC) const {
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return RC != this && hasSubClassEq(RC);
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}
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/// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
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/// class.
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bool hasSubClassEq(const TargetRegisterClass *RC) const {
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unsigned ID = RC->getID();
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return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
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}
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/// hasSuperClass - return true if the specified TargetRegisterClass is a
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/// proper super-class of this TargetRegisterClass.
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bool hasSuperClass(const TargetRegisterClass *RC) const {
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return RC->hasSubClass(this);
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}
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/// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
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/// class.
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bool hasSuperClassEq(const TargetRegisterClass *RC) const {
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return RC->hasSubClassEq(this);
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}
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/// getSubClassMask - Returns a bit vector of subclasses, including this one.
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/// The vector is indexed by class IDs, see hasSubClassEq() above for how to
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/// use it.
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const unsigned *getSubClassMask() const {
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return SubClassMask;
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}
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/// getSuperClasses - Returns a NULL terminated list of super-classes. The
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/// classes are ordered by ID which is also a topological ordering from large
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/// to small classes. The list does NOT include the current class.
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sc_iterator getSuperClasses() const {
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return SuperClasses;
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}
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/// isASubClass - return true if this TargetRegisterClass is a subset
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/// class of at least one other TargetRegisterClass.
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bool isASubClass() const {
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return SuperClasses[0] != 0;
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}
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/// getRawAllocationOrder - Returns the preferred order for allocating
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/// registers from this register class in MF. The raw order comes directly
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/// from the .td file and may include reserved registers that are not
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/// allocatable. Register allocators should also make sure to allocate
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/// callee-saved registers only after all the volatiles are used. The
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/// RegisterClassInfo class provides filtered allocation orders with
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/// callee-saved registers moved to the end.
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///
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/// The MachineFunction argument can be used to tune the allocatable
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/// registers based on the characteristics of the function, subtarget, or
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/// other criteria.
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///
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/// By default, this method returns all registers in the class.
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///
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virtual
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ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
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return makeArrayRef(begin(), getNumRegs());
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}
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};
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/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
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/// registers. These are used by codegen, not by MC.
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struct TargetRegisterInfoDesc {
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unsigned CostPerUse; // Extra cost of instructions using register.
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bool inAllocatableClass; // Register belongs to an allocatable regclass.
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};
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/// TargetRegisterInfo base class - We assume that the target defines a static
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/// array of TargetRegisterDesc objects that represent all of the machine
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/// registers that the target has. As such, we simply have to track a pointer
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/// to this array so that we can turn register number into a register
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/// descriptor.
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///
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class TargetRegisterInfo : public MCRegisterInfo {
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public:
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typedef const TargetRegisterClass * const * regclass_iterator;
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private:
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const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
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const char *const *SubRegIndexNames; // Names of subreg indexes.
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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protected:
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TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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regclass_iterator RegClassBegin,
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regclass_iterator RegClassEnd,
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const char *const *subregindexnames);
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virtual ~TargetRegisterInfo();
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public:
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// Register numbers can represent physical registers, virtual registers, and
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// sometimes stack slots. The unsigned values are divided into these ranges:
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//
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// 0 Not a register, can be used as a sentinel.
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// [1;2^30) Physical registers assigned by TableGen.
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// [2^30;2^31) Stack slots. (Rarely used.)
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// [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
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//
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// Further sentinels can be allocated from the small negative integers.
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// DenseMapInfo<unsigned> uses -1u and -2u.
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/// isStackSlot - Sometimes it is useful the be able to store a non-negative
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/// frame index in a variable that normally holds a register. isStackSlot()
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/// returns true if Reg is in the range used for stack slots.
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///
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/// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
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/// slots, so if a variable may contains a stack slot, always check
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/// isStackSlot() first.
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///
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static bool isStackSlot(unsigned Reg) {
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return int(Reg) >= (1 << 30);
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}
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/// stackSlot2Index - Compute the frame index from a register value
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/// representing a stack slot.
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static int stackSlot2Index(unsigned Reg) {
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assert(isStackSlot(Reg) && "Not a stack slot");
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return int(Reg - (1u << 30));
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}
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/// index2StackSlot - Convert a non-negative frame index to a stack slot
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/// register value.
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static unsigned index2StackSlot(int FI) {
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assert(FI >= 0 && "Cannot hold a negative frame index.");
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return FI + (1u << 30);
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}
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/// isPhysicalRegister - Return true if the specified register number is in
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/// the physical register namespace.
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static bool isPhysicalRegister(unsigned Reg) {
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assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
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return int(Reg) > 0;
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}
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/// isVirtualRegister - Return true if the specified register number is in
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/// the virtual register namespace.
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static bool isVirtualRegister(unsigned Reg) {
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assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
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return int(Reg) < 0;
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}
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/// virtReg2Index - Convert a virtual register number to a 0-based index.
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/// The first virtual register in a function will get the index 0.
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static unsigned virtReg2Index(unsigned Reg) {
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assert(isVirtualRegister(Reg) && "Not a virtual register");
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return Reg & ~(1u << 31);
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}
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/// index2VirtReg - Convert a 0-based index to a virtual register number.
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/// This is the inverse operation of VirtReg2IndexFunctor below.
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static unsigned index2VirtReg(unsigned Index) {
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return Index | (1u << 31);
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}
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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const TargetRegisterClass *
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getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
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/// getAllocatableSet - Returns a bitset indexed by register number
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/// indicating if a register is allocatable or not. If a register class is
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/// specified, returns the subset for the class.
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BitVector getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC = NULL) const;
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/// getCostPerUse - Return the additional cost of using this register instead
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/// of other registers in its class.
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unsigned getCostPerUse(unsigned RegNo) const {
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return InfoDesc[RegNo].CostPerUse;
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}
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/// isInAllocatableClass - Return true if the register is in the allocation
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/// of any register class.
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bool isInAllocatableClass(unsigned RegNo) const {
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return InfoDesc[RegNo].inAllocatableClass;
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}
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/// getSubRegIndexName - Return the human-readable symbolic target-specific
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/// name for the specified SubRegIndex.
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const char *getSubRegIndexName(unsigned SubIdx) const {
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assert(SubIdx && "This is not a subregister index");
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return SubRegIndexNames[SubIdx-1];
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}
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/// regsOverlap - Returns true if the two registers are equal or alias each
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/// other. The registers may be virtual register.
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bool regsOverlap(unsigned regA, unsigned regB) const {
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if (regA == regB) return true;
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if (isVirtualRegister(regA) || isVirtualRegister(regB))
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return false;
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for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
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if (*regList == regB) return true;
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}
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return false;
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}
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/// isSubRegister - Returns true if regB is a sub-register of regA.
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///
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bool isSubRegister(unsigned regA, unsigned regB) const {
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return isSuperRegister(regB, regA);
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}
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/// isSuperRegister - Returns true if regB is a super-register of regA.
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///
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bool isSuperRegister(unsigned regA, unsigned regB) const {
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for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
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if (*regList == regB) return true;
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}
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return false;
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}
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee saved registers on this target. The register should be in the
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/// order of desired callee-save stack frame offset. The first register is
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/// closed to the incoming stack pointer if stack grows down, and vice versa.
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virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
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const = 0;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses
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/// and should be considered unavailable at all times, e.g. SP, RA. This is
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/// used by register scavenger to determine what registers are free.
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virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
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/// getSubReg - Returns the physical register number of sub-register "Index"
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/// for physical register RegNo. Return zero if the sub-register does not
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/// exist.
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virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
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/// getSubRegIndex - For a given register pair, return the sub-register index
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/// if the second register is a sub-register of the first. Return zero
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/// otherwise.
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virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
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/// getMatchingSuperReg - Return a super-register of the specified register
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/// Reg so its sub-register of index SubIdx is Reg.
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unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
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const TargetRegisterClass *RC) const {
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for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
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if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
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return SR;
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return 0;
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}
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/// canCombineSubRegIndices - Given a register class and a list of
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/// subregister indices, return true if it's possible to combine the
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/// subregister indices into one that corresponds to a larger
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/// subregister. Return the new subregister index by reference. Note the
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/// new index may be zero if the given subregisters can be combined to
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/// form the whole register.
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virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const {
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return 0;
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}
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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virtual const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const {
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return 0;
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}
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/// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
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/// supports the sub-register index Idx.
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/// If no such sub-class exists, return NULL.
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/// If all registers in RC already have an Idx sub-register, return RC.
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///
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/// TableGen generates a version of this function that is good enough in most
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/// cases. Targets can override if they have constraints that TableGen
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/// doesn't understand. For example, the x86 sub_8bit sub-register index is
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/// supported by the full GR32 register class in 64-bit mode, but only by the
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/// GR32_ABCD regiister class in 32-bit mode.
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///
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virtual const TargetRegisterClass *
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getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
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/// composeSubRegIndices - Return the subregister index you get from composing
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/// two subregister indices.
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///
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/// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
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/// returns c. Note that composeSubRegIndices does not tell you about illegal
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/// compositions. If R does not have a subreg a, or R:a does not have a subreg
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/// b, composeSubRegIndices doesn't tell you.
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///
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/// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
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/// ssub_0:S0 - ssub_3:S3 subregs.
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/// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
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///
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virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
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// This default implementation is correct for most targets.
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return b;
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}
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//===--------------------------------------------------------------------===//
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// Register Class Information
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//
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/// Register class iterators
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///
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regclass_iterator regclass_begin() const { return RegClassBegin; }
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regclass_iterator regclass_end() const { return RegClassEnd; }
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unsigned getNumRegClasses() const {
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return (unsigned)(regclass_end()-regclass_begin());
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}
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/// getRegClass - Returns the register class associated with the enumeration
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/// value. See class MCOperandInfo.
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const TargetRegisterClass *getRegClass(unsigned i) const {
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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return RegClassBegin[i];
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}
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/// getCommonSubClass - find the largest common subclass of A and B. Return
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/// NULL if there is no common subclass.
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const TargetRegisterClass *
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getCommonSubClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B) const;
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values. If a target supports multiple different pointer register classes,
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/// kind specifies which one is indicated.
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virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
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assert(0 && "Target didn't implement getPointerRegClass!");
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return 0; // Must return a value in order to compile with VS 2005
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}
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. If it is possible to copy the register
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/// directly without using a cross register class copy, return the specified
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/// RC. Returns NULL if it is not possible to copy between a two registers of
|
|
/// the specified class.
|
|
virtual const TargetRegisterClass *
|
|
getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
|
return RC;
|
|
}
|
|
|
|
/// getLargestLegalSuperClass - Returns the largest super class of RC that is
|
|
/// legal to use in the current sub-target and has the same spill size.
|
|
/// The returned register class can be used to create virtual registers which
|
|
/// means that all its registers can be copied and spilled.
|
|
virtual const TargetRegisterClass*
|
|
getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
|
|
/// The default implementation is very conservative and doesn't allow the
|
|
/// register allocator to inflate register classes.
|
|
return RC;
|
|
}
|
|
|
|
/// getRegPressureLimit - Return the register pressure "high water mark" for
|
|
/// the specific register class. The scheduler is in high register pressure
|
|
/// mode (for the specific register class) if it goes over the limit.
|
|
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const {
|
|
return 0;
|
|
}
|
|
|
|
/// getRawAllocationOrder - Returns the register allocation order for a
|
|
/// specified register class with a target-dependent hint. The returned list
|
|
/// may contain reserved registers that cannot be allocated.
|
|
///
|
|
/// Register allocators need only call this function to resolve
|
|
/// target-dependent hints, but it should work without hinting as well.
|
|
virtual ArrayRef<unsigned>
|
|
getRawAllocationOrder(const TargetRegisterClass *RC,
|
|
unsigned HintType, unsigned HintReg,
|
|
const MachineFunction &MF) const {
|
|
return RC->getRawAllocationOrder(MF);
|
|
}
|
|
|
|
/// ResolveRegAllocHint - Resolves the specified register allocation hint
|
|
/// to a physical register. Returns the physical register if it is successful.
|
|
virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
|
|
const MachineFunction &MF) const {
|
|
if (Type == 0 && Reg && isPhysicalRegister(Reg))
|
|
return Reg;
|
|
return 0;
|
|
}
|
|
|
|
/// avoidWriteAfterWrite - Return true if the register allocator should avoid
|
|
/// writing a register from RC in two consecutive instructions.
|
|
/// This can avoid pipeline stalls on certain architectures.
|
|
/// It does cause increased register pressure, though.
|
|
virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
|
|
return false;
|
|
}
|
|
|
|
/// UpdateRegAllocHint - A callback to allow target a chance to update
|
|
/// register allocation hints when a register is "changed" (e.g. coalesced)
|
|
/// to another register. e.g. On ARM, some virtual registers should target
|
|
/// register pairs, if one of pair is coalesced to another register, the
|
|
/// allocation hint of the other half of the pair should be changed to point
|
|
/// to the new register.
|
|
virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
|
|
MachineFunction &MF) const {
|
|
// Do nothing.
|
|
}
|
|
|
|
/// requiresRegisterScavenging - returns true if the target requires (and can
|
|
/// make use of) the register scavenger.
|
|
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// useFPForScavengingIndex - returns true if the target wants to use
|
|
/// frame pointer based accesses to spill to the scavenger emergency spill
|
|
/// slot.
|
|
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
/// requiresFrameIndexScavenging - returns true if the target requires post
|
|
/// PEI scavenging of registers for materializing frame index constants.
|
|
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// requiresVirtualBaseRegisters - Returns true if the target wants the
|
|
/// LocalStackAllocation pass to be run and virtual base registers
|
|
/// used for more efficient stack access.
|
|
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// hasReservedSpillSlot - Return true if target has reserved a spill slot in
|
|
/// the stack frame of the given function for the specified register. e.g. On
|
|
/// x86, if the frame register is required, the first fixed stack object is
|
|
/// reserved as its spill slot. This tells PEI not to create a new stack frame
|
|
/// object for the given register. It should be called only after
|
|
/// processFunctionBeforeCalleeSavedScan().
|
|
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
|
|
int &FrameIdx) const {
|
|
return false;
|
|
}
|
|
|
|
/// needsStackRealignment - true if storage within the function requires the
|
|
/// stack pointer to be aligned more than the normal calling convention calls
|
|
/// for.
|
|
virtual bool needsStackRealignment(const MachineFunction &MF) const {
|
|
return false;
|
|
}
|
|
|
|
/// getFrameIndexInstrOffset - Get the offset from the referenced frame
|
|
/// index in the instruction, if there is one.
|
|
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
|
|
int Idx) const {
|
|
return 0;
|
|
}
|
|
|
|
/// needsFrameBaseReg - Returns true if the instruction's frame index
|
|
/// reference would be better served by a base register other than FP
|
|
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
|
|
/// references it should create new base registers for.
|
|
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
|
|
return false;
|
|
}
|
|
|
|
/// materializeFrameBaseRegister - Insert defining instruction(s) for
|
|
/// BaseReg to be a pointer to FrameIdx before insertion point I.
|
|
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
|
unsigned BaseReg, int FrameIdx,
|
|
int64_t Offset) const {
|
|
assert(0 && "materializeFrameBaseRegister does not exist on this target");
|
|
}
|
|
|
|
/// resolveFrameIndex - Resolve a frame index operand of an instruction
|
|
/// to reference the indicated base register plus offset instead.
|
|
virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
unsigned BaseReg, int64_t Offset) const {
|
|
assert(0 && "resolveFrameIndex does not exist on this target");
|
|
}
|
|
|
|
/// isFrameOffsetLegal - Determine whether a given offset immediate is
|
|
/// encodable to resolve a frame index.
|
|
virtual bool isFrameOffsetLegal(const MachineInstr *MI,
|
|
int64_t Offset) const {
|
|
assert(0 && "isFrameOffsetLegal does not exist on this target");
|
|
return false; // Must return a value in order to compile with VS 2005
|
|
}
|
|
|
|
/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
|
|
/// code insertion to eliminate call frame setup and destroy pseudo
|
|
/// instructions (but only if the Target is using them). It is responsible
|
|
/// for eliminating these instructions, replacing them with concrete
|
|
/// instructions. This method need only be implemented if using call frame
|
|
/// setup/destroy pseudo instructions.
|
|
///
|
|
virtual void
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const {
|
|
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
|
|
}
|
|
|
|
|
|
/// saveScavengerRegister - Spill the register so it can be used by the
|
|
/// register scavenger. Return true if the register was spilled, false
|
|
/// otherwise. If this function does not spill the register, the scavenger
|
|
/// will instead spill it to the emergency spill slot.
|
|
///
|
|
virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
MachineBasicBlock::iterator &UseMI,
|
|
const TargetRegisterClass *RC,
|
|
unsigned Reg) const {
|
|
return false;
|
|
}
|
|
|
|
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
|
|
/// frame indices from instructions which may use them. The instruction
|
|
/// referenced by the iterator contains an MO_FrameIndex operand which must be
|
|
/// eliminated by this method. This method may modify or replace the
|
|
/// specified instruction, as long as it keeps the iterator pointing at the
|
|
/// finished product. SPAdj is the SP adjustment due to call frame setup
|
|
/// instruction.
|
|
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
|
int SPAdj, RegScavenger *RS=NULL) const = 0;
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
/// Debug information queries.
|
|
|
|
/// getFrameRegister - This method should return the register used as a base
|
|
/// for values allocated in the current stack frame.
|
|
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
|
|
|
|
/// getCompactUnwindRegNum - This function maps the register to the number for
|
|
/// compact unwind encoding. Return -1 if the register isn't valid.
|
|
virtual int getCompactUnwindRegNum(unsigned, bool) const {
|
|
return -1;
|
|
}
|
|
};
|
|
|
|
|
|
// This is useful when building IndexedMaps keyed on virtual registers
|
|
struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
|
|
unsigned operator()(unsigned Reg) const {
|
|
return TargetRegisterInfo::virtReg2Index(Reg);
|
|
}
|
|
};
|
|
|
|
/// PrintReg - Helper class for printing registers on a raw_ostream.
|
|
/// Prints virtual and physical registers with or without a TRI instance.
|
|
///
|
|
/// The format is:
|
|
/// %noreg - NoRegister
|
|
/// %vreg5 - a virtual register.
|
|
/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
|
|
/// %EAX - a physical register
|
|
/// %physreg17 - a physical register when no TRI instance given.
|
|
///
|
|
/// Usage: OS << PrintReg(Reg, TRI) << '\n';
|
|
///
|
|
class PrintReg {
|
|
const TargetRegisterInfo *TRI;
|
|
unsigned Reg;
|
|
unsigned SubIdx;
|
|
public:
|
|
PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
|
|
: TRI(tri), Reg(reg), SubIdx(subidx) {}
|
|
void print(raw_ostream&) const;
|
|
};
|
|
|
|
static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
|
|
PR.print(OS);
|
|
return OS;
|
|
}
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|