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https://github.com/c64scene-ar/llvm-6502.git
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115fd30b24
LCSSA when we promote to SSA registers inside of LICM. Currently, this is actually necessary. The promotion logic in LICM uses SSAUpdater which doesn't understand how to place LCSSA PHI nodes. Teaching it to do so would be a very significant undertaking. It may be worthwhile and I've left a FIXME about this in the code as well as starting a thread on llvmdev to try to figure out the right long-term solution. For now, the PR needs to be fixed. Short of using the promition SSAUpdater to place both the LCSSA PHI nodes and the promoted PHI nodes, I don't see a cleaner or cheaper way of achieving this. Fortunately, LCSSA is relatively lazy and sparse -- it should only update instructions which need it. We can also skip the recursive variant when we don't promote to SSA values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200612 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.2 KiB
LLVM
77 lines
2.2 KiB
LLVM
; RUN: opt -S -basicaa -licm < %s | FileCheck %s
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;
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; Manually validate LCSSA form is preserved even after SSAUpdater is used to
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; promote things in the loop bodies.
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@x = common global i32 0, align 4
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@y = common global i32 0, align 4
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define void @PR18688() {
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; CHECK-LABEL: @PR18688(
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entry:
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br i1 undef, label %return, label %outer.preheader
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outer.preheader:
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br label %outer.header
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; CHECK: outer.preheader:
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; CHECK: br label %outer.header
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outer.header:
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store i32 0, i32* @x, align 4
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br i1 undef, label %outer.latch, label %inner.preheader
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; CHECK: outer.header:
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; CHECK-NEXT: br i1 undef, label %outer.latch, label %inner.preheader
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inner.preheader:
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br label %inner.header
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; CHECK: inner.preheader:
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; CHECK-NEXT: br label %inner.header
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inner.header:
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br i1 undef, label %inner.body.rhs, label %inner.latch
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; CHECK: inner.header:
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; CHECK-NEXT: %[[PHI0:[^,]+]] = phi i32 [ %{{[^,]+}}, %inner.latch ], [ 0, %inner.preheader ]
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; CHECK-NEXT: br i1 undef, label %inner.body.rhs, label %inner.latch
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inner.body.rhs:
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store i32 0, i32* @x, align 4
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br label %inner.latch
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; CHECK: inner.body.rhs:
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; CHECK-NEXT: br label %inner.latch
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inner.latch:
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%y_val = load i32* @y, align 4
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%icmp = icmp eq i32 %y_val, 0
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br i1 %icmp, label %inner.exit, label %inner.header
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; CHECK: inner.latch:
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; CHECK-NEXT: %[[PHI1:[^,]+]] = phi i32 [ 0, %inner.body.rhs ], [ %[[PHI0]], %inner.header ]
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; CHECK-NEXT: br i1 %{{[^,]+}}, label %inner.exit, label %inner.header
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inner.exit:
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br label %outer.latch
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; CHECK: inner.exit:
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; CHECK-NEXT: %[[INNER_LCSSA:[^,]+]] = phi i32 [ %[[PHI1]], %inner.latch ]
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; CHECK-NEXT: br label %outer.latch
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outer.latch:
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br i1 undef, label %outer.exit, label %outer.header
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; CHECK: outer.latch:
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; CHECK-NEXT: %[[PHI2:[^,]+]] = phi i32 [ %[[INNER_LCSSA]], %inner.exit ], [ 0, %outer.header ]
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; CHECK-NEXT: br i1 {{.*}}, label %outer.exit, label %outer.header
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outer.exit:
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br label %return
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; CHECK: outer.exit:
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; CHECK-NEXT: %[[OUTER_LCSSA:[^,]+]] = phi i32 [ %[[PHI2]], %outer.latch ]
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; CHECK-NEXT: store i32 %[[OUTER_LCSSA]]
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; CHECK-NEXT: br label %return
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return:
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ret void
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}
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