mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-02 11:30:10 +00:00
8395251c0a
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
340 lines
18 KiB
TableGen
340 lines
18 KiB
TableGen
// Bitcasts between 512-bit vector types. Return the original type since
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// no instruction is needed for the conversion
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let Predicates = [HasAVX512] in {
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def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
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def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
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def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
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def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
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def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
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def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
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def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
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def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
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def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
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def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
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def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
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def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
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def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
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def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
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def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
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def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
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def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
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def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
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def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
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def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
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def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
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def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
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def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
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def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
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def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
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def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
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def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
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def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
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def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
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def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
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def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
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def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
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def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
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def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
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def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
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def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
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def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
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def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
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def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
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// Bitcasts between 256-bit vector types. Return the original type since
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// no instruction is needed for the conversion
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def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
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def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
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def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
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def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
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def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
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def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
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def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
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def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
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def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
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def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
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def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
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def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
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def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
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def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
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def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
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def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
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def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
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def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
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def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
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def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
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def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
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def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
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def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
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def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
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def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
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def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
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def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
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def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
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def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
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def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
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}
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//===----------------------------------------------------------------------===//
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// AVX-512 - VECTOR INSERT
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//
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// -- 32x8 form --
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let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
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def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
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(ins VR512:$src1, VR128X:$src2, i8imm:$src3),
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"vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512;
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let mayLoad = 1 in
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def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
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(ins VR512:$src1, f128mem:$src2, i8imm:$src3),
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"vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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}
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// -- 64x4 fp form --
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let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
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def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
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(ins VR512:$src1, VR256X:$src2, i8imm:$src3),
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"vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512, VEX_W;
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let mayLoad = 1 in
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def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
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(ins VR512:$src1, i256mem:$src2, i8imm:$src3),
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"vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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}
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// -- 32x4 integer form --
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let neverHasSideEffects = 1 in {
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def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
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(ins VR512:$src1, VR128X:$src2, i8imm:$src3),
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"vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512;
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let mayLoad = 1 in
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def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
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(ins VR512:$src1, i128mem:$src2, i8imm:$src3),
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"vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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}
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let neverHasSideEffects = 1 in {
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// -- 64x4 form --
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def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
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(ins VR512:$src1, VR256X:$src2, i8imm:$src3),
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"vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512, VEX_W;
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let mayLoad = 1 in
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def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
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(ins VR512:$src1, i256mem:$src2, i8imm:$src3),
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"vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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}
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def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
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(iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
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(iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
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(iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
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(iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
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(iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
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(bc_v4i32 (loadv2i64 addr:$src2)),
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(iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
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(iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
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(iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert128_imm VR512:$ins))>;
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def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
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(iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
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(iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
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(iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
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(iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
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(iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
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(iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
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(iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
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(bc_v8i32 (loadv4i64 addr:$src2)),
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(iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
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(INSERT_get_vinsert256_imm VR512:$ins))>;
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// vinsertps - insert f32 to XMM
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def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
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(ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
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!strconcat("vinsertps{z}",
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
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EVEX_4V;
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def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
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(ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
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!strconcat("vinsertps{z}",
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128X:$dst, (X86insrtps VR128X:$src1,
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(v4f32 (scalar_to_vector (loadf32 addr:$src2))),
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imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
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//===----------------------------------------------------------------------===//
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// AVX-512 VECTOR EXTRACT
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//---
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let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
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// -- 32x4 form --
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def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512;
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def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
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(ins f128mem:$dst, VR512:$src1, i8imm:$src2),
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"vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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// -- 64x4 form --
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def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W;
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let mayStore = 1 in
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def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
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(ins f256mem:$dst, VR512:$src1, i8imm:$src2),
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"vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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}
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let neverHasSideEffects = 1 in {
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// -- 32x4 form --
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def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512;
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def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
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(ins i128mem:$dst, VR512:$src1, i8imm:$src2),
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"vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
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// -- 64x4 form --
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def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
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(ins VR512:$src1, i8imm:$src2),
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"vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W;
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let mayStore = 1 in
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def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
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(ins i256mem:$dst, VR512:$src1, i8imm:$src2),
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"vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[]>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
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}
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def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
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(v4f32 (VEXTRACTF32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
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(v4i32 (VEXTRACTF32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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|
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def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
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(v2f64 (VEXTRACTF32x4rr VR512:$src1,
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(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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|
|
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def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
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(v2i64 (VEXTRACTI32x4rr VR512:$src1,
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|
(EXTRACT_get_vextract128_imm VR128X:$ext)))>;
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|
|
|
|
|
def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
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(v8f32 (VEXTRACTF64x4rr VR512:$src1,
|
|
(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
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|
|
|
def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
|
|
(v8i32 (VEXTRACTI64x4rr VR512:$src1,
|
|
(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
|
|
|
|
def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
|
|
(v4f64 (VEXTRACTF64x4rr VR512:$src1,
|
|
(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
|
|
|
|
def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
|
|
(v4i64 (VEXTRACTI64x4rr VR512:$src1,
|
|
(EXTRACT_get_vextract256_imm VR256X:$ext)))>;
|
|
|
|
// A 256-bit subvector extract from the first 512-bit vector position
|
|
// is a subregister copy that needs no instruction.
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|
def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
|
|
(v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
|
|
def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
|
|
(v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
|
|
def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
|
|
(v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
|
|
def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
|
|
(v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
|
|
|
|
// zmm -> xmm
|
|
def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
|
|
(v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
|
|
def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
|
|
(v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
|
|
def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
|
|
(v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
|
|
def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
|
|
(v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
|
|
|
|
|
|
// A 128-bit subvector insert to the first 512-bit vector position
|
|
// is a subregister copy that needs no instruction.
|
|
def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
|
|
(INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
|
|
sub_ymm)>;
|
|
def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
|
|
(INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
|
|
sub_ymm)>;
|
|
def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
|
|
(INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
|
|
sub_ymm)>;
|
|
def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
|
|
(INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
|
|
sub_ymm)>;
|
|
|
|
def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
|
|
def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
|
|
def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
|
|
def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
|
|
(INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
|
|
|