Renato Golin 0966a4e370 Adding support to LLVM for targeting Cortex-A72 ... Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228140 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-04 13:31:29 +00:00
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AArch64	Adding support to LLVM for targeting Cortex-A72	2015-02-04 13:31:29 +00:00
ARM	Adding support to LLVM for targeting Cortex-A72	2015-02-04 13:31:29 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Converting XTYPE/SHIFT intrinsics. Cleaning out old intrinsic patterns and updating tests.	2015-02-03 20:40:52 +00:00
Inputs
Mips	Move the Mips target to storing the ABI in the TargetMachine rather	2015-01-26 17:33:46 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Handle 32-bit targets properly in PPCTLSDynamicCall.cpp	2015-02-04 05:51:56 +00:00
R600	R600/SI: Remove the -CHECK suffix from all FileCheck prefixes in LIT tests	2015-02-03 21:53:27 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[x86] Give movss and movsd execution domains in the x86 backend.	2015-02-04 10:58:53 +00:00
XCore