llvm-6502/test/CodeGen/ARM64/vcvtxd_f32_f64.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

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306 B
LLVM

; RUN: llc < %s -march=arm64 | FileCheck %s
define float @fcvtxn(double %a) {
; CHECK-LABEL: fcvtxn:
; CHECK: fcvtxn s0, d0
; CHECK-NEXT: ret
%vcvtxd.i = tail call float @llvm.arm64.sisd.fcvtxn(double %a) nounwind
ret float %vcvtxd.i
}
declare float @llvm.arm64.sisd.fcvtxn(double) nounwind readnone