mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
fc210ac1ef
Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
458 lines
14 KiB
LLVM
458 lines
14 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
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define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: add_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fadd <4 x float> %1, %2
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; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size add_v4f32
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}
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define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: add_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fadd <2 x double> %1, %2
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; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size add_v2f64
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}
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define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: sub_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fsub <4 x float> %1, %2
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; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v4f32
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}
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define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: sub_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fsub <2 x double> %1, %2
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; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size sub_v2f64
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}
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define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: mul_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fmul <4 x float> %1, %2
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; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v4f32
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}
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define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: mul_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fmul <2 x double> %1, %2
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; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size mul_v2f64
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}
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define void @fma_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
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<4 x float>* %c) nounwind {
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; CHECK: fma_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = load <4 x float>* %c
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; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
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%4 = tail call <4 x float> @llvm.fma.v4f32 (<4 x float> %1, <4 x float> %2,
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<4 x float> %3)
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; CHECK-DAG: fmadd.w [[R1]], [[R2]], [[R3]]
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store <4 x float> %4, <4 x float>* %d
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK: .size fma_v4f32
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}
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define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
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<2 x double>* %c) nounwind {
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; CHECK: fma_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = load <2 x double>* %c
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
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%4 = tail call <2 x double> @llvm.fma.v2f64 (<2 x double> %1, <2 x double> %2,
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<2 x double> %3)
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; CHECK-DAG: fmadd.d [[R1]], [[R2]], [[R3]]
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store <2 x double> %4, <2 x double>* %d
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; CHECK-DAG: st.d [[R1]], 0($4)
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ret void
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; CHECK: .size fma_v2f64
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}
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define void @fmsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
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<4 x float>* %c) nounwind {
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; CHECK: fmsub_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = load <4 x float>* %c
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; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
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%4 = fmul <4 x float> %2, %3
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%5 = fsub <4 x float> %1, %4
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; CHECK-DAG: fmsub.w [[R1]], [[R2]], [[R3]]
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store <4 x float> %5, <4 x float>* %d
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; CHECK-DAG: st.w [[R1]], 0($4)
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ret void
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; CHECK: .size fmsub_v4f32
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}
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define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
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<2 x double>* %c) nounwind {
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; CHECK: fmsub_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = load <2 x double>* %c
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
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%4 = fmul <2 x double> %2, %3
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%5 = fsub <2 x double> %1, %4
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; CHECK-DAG: fmsub.d [[R1]], [[R2]], [[R3]]
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store <2 x double> %5, <2 x double>* %d
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; CHECK-DAG: st.d [[R1]], 0($4)
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ret void
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; CHECK: .size fmsub_v2f64
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}
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define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
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; CHECK: fdiv_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = load <4 x float>* %b
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; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
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%3 = fdiv <4 x float> %1, %2
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; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size fdiv_v4f32
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}
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define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
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; CHECK: fdiv_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = load <2 x double>* %b
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; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
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%3 = fdiv <2 x double> %1, %2
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; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size fdiv_v2f64
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}
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define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
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; CHECK: fabs_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1)
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; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
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store <4 x float> %2, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size fabs_v4f32
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}
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define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
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; CHECK: fabs_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1)
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; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]]
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store <2 x double> %2, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size fabs_v2f64
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}
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define void @fexp2_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
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; CHECK: fexp2_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)
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; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
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; CHECK-DAG: ffint_u.w [[R4:\$w[0-9]+]], [[R3]]
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; CHECK-DAG: fexp2.w [[R4:\$w[0-9]+]], [[R3]], [[R1]]
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store <4 x float> %2, <4 x float>* %c
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; CHECK-DAG: st.w [[R4]], 0($4)
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ret void
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; CHECK: .size fexp2_v4f32
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}
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define void @fexp2_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
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; CHECK: fexp2_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
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; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
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; CHECK-DAG: ffint_u.d [[R4:\$w[0-9]+]], [[R3]]
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; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]]
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store <2 x double> %2, <2 x double>* %c
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; CHECK-DAG: st.d [[R4]], 0($4)
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ret void
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; CHECK: .size fexp2_v2f64
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}
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define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind {
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; CHECK: fexp2_v4f32_2:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)
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%3 = fmul <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, %2
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; CHECK-DAG: lui [[R3:\$[0-9]+]], 16384
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; CHECK-DAG: fill.w [[R4:\$w[0-9]+]], [[R3]]
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; CHECK-DAG: fexp2.w [[R5:\$w[0-9]+]], [[R4]], [[R1]]
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store <4 x float> %3, <4 x float>* %c
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; CHECK-DAG: st.w [[R5]], 0($4)
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ret void
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; CHECK: .size fexp2_v4f32_2
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}
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define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
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; CHECK: .8byte 4611686018427387904
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; CHECK-NEXT: .8byte 4611686018427387904
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; CHECK: fexp2_v2f64_2:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
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%3 = fmul <2 x double> <double 2.0, double 2.0>, %2
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; CHECK-DAG: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[G_PTR]])
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; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]]
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store <2 x double> %3, <2 x double>* %c
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; CHECK-DAG: st.d [[R4]], 0($4)
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ret void
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; CHECK: .size fexp2_v2f64_2
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}
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define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
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; CHECK: fsqrt_v4f32:
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%1 = load <4 x float>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1)
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; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]]
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store <4 x float> %2, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size fsqrt_v4f32
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}
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define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
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; CHECK: fsqrt_v2f64:
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%1 = load <2 x double>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1)
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; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]]
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store <2 x double> %2, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size fsqrt_v2f64
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}
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define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
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; CHECK: ffint_u_v4f32:
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%1 = load <4 x i32>* %a
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; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
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%2 = uitofp <4 x i32> %1 to <4 x float>
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; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]]
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store <4 x float> %2, <4 x float>* %c
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; CHECK-DAG: st.w [[R3]], 0($4)
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ret void
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; CHECK: .size ffint_u_v4f32
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}
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define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
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; CHECK: ffint_u_v2f64:
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%1 = load <2 x i64>* %a
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; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
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%2 = uitofp <2 x i64> %1 to <2 x double>
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; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]]
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store <2 x double> %2, <2 x double>* %c
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; CHECK-DAG: st.d [[R3]], 0($4)
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ret void
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; CHECK: .size ffint_u_v2f64
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}
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define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
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; CHECK: ffint_s_v4f32:
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%1 = load <4 x i32>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = sitofp <4 x i32> %1 to <4 x float>
|
|
; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]]
|
|
store <4 x float> %2, <4 x float>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size ffint_s_v4f32
|
|
}
|
|
|
|
define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
|
|
; CHECK: ffint_s_v2f64:
|
|
|
|
%1 = load <2 x i64>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = sitofp <2 x i64> %1 to <2 x double>
|
|
; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]]
|
|
store <2 x double> %2, <2 x double>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size ffint_s_v2f64
|
|
}
|
|
|
|
define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
|
|
; CHECK: ftrunc_u_v4f32:
|
|
|
|
%1 = load <4 x float>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = fptoui <4 x float> %1 to <4 x i32>
|
|
; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]]
|
|
store <4 x i32> %2, <4 x i32>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size ftrunc_u_v4f32
|
|
}
|
|
|
|
define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
|
|
; CHECK: ftrunc_u_v2f64:
|
|
|
|
%1 = load <2 x double>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = fptoui <2 x double> %1 to <2 x i64>
|
|
; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]]
|
|
store <2 x i64> %2, <2 x i64>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size ftrunc_u_v2f64
|
|
}
|
|
|
|
define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
|
|
; CHECK: ftrunc_s_v4f32:
|
|
|
|
%1 = load <4 x float>* %a
|
|
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = fptosi <4 x float> %1 to <4 x i32>
|
|
; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]]
|
|
store <4 x i32> %2, <4 x i32>* %c
|
|
; CHECK-DAG: st.w [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size ftrunc_s_v4f32
|
|
}
|
|
|
|
define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
|
|
; CHECK: ftrunc_s_v2f64:
|
|
|
|
%1 = load <2 x double>* %a
|
|
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
|
|
%2 = fptosi <2 x double> %1 to <2 x i64>
|
|
; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]]
|
|
store <2 x i64> %2, <2 x i64>* %c
|
|
; CHECK-DAG: st.d [[R3]], 0($4)
|
|
|
|
ret void
|
|
; CHECK: .size ftrunc_s_v2f64
|
|
}
|
|
|
|
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val)
|
|
declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val)
|
|
declare <4 x float> @llvm.exp2.v4f32(<4 x float> %val)
|
|
declare <2 x double> @llvm.exp2.v2f64(<2 x double> %val)
|
|
declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b,
|
|
<4 x float> %c)
|
|
declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,
|
|
<2 x double> %c)
|
|
declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val)
|
|
declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val)
|