mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ca795b61be
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
6.1 KiB
LLVM
139 lines
6.1 KiB
LLVM
; RUN: llc -march=mips < %s
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
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; RUN: llc -march=mipsel < %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
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; This test originally failed for MSA with a
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; `Opc && "Cannot copy registers"' assertion.
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; It should at least successfully build.
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define void @autogen_SD1935737938(i8*, i32*, i64*, i32, i64, i8) {
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BB:
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%A4 = alloca i64
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%A3 = alloca <4 x i32>
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%A2 = alloca i64
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%A1 = alloca i32
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%A = alloca <2 x i64>
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%L = load i8* %0
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store i8 -1, i8* %0
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%E = extractelement <2 x i32> zeroinitializer, i32 0
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%Shuff = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%I = insertelement <1 x i64> <i64 -1>, i64 286689, i32 0
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%B = lshr i8 %L, -69
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%ZE = fpext float 0xBF2AA5FE80000000 to double
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%Sl = select i1 true, <1 x i64> <i64 -1>, <1 x i64> <i64 -1>
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%L5 = load i8* %0
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store i8 -69, i8* %0
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%E6 = extractelement <16 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i32 14
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%Shuff7 = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%I8 = insertelement <2 x i32> zeroinitializer, i32 135673, i32 1
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%B9 = udiv i8 %B, %B
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%FC = uitofp i32 %3 to double
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%Sl10 = select i1 true, <1 x i1> zeroinitializer, <1 x i1> zeroinitializer
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%Cmp = icmp ne <1 x i64> %I, <i64 -1>
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%L11 = load i8* %0
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store i8 %L11, i8* %0
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%E12 = extractelement <1 x i64> <i64 -1>, i32 0
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%Shuff13 = shufflevector <1 x i64> %Sl, <1 x i64> <i64 -1>, <1 x i32> <i32 1>
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%I14 = insertelement <1 x i64> %I, i64 303290, i32 0
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%B15 = frem float 0.000000e+00, 0.000000e+00
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%Sl16 = select i1 true, <1 x i1> %Cmp, <1 x i1> zeroinitializer
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%Cmp17 = fcmp one float 0xBD946F9840000000, %B15
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br label %CF74
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CF74: ; preds = %CF74, %CF80, %CF76, %BB
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%L18 = load i8* %0
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store i8 -69, i8* %0
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%E19 = extractelement <1 x i64> %Sl, i32 0
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%Shuff20 = shufflevector <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i32> <i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10>
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%I21 = insertelement <2 x i32> %Shuff, i32 135673, i32 0
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%B22 = urem i32 135673, %3
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%FC23 = sitofp i8 %L to float
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%Sl24 = select i1 true, i8 %B, i8 %L18
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%L25 = load i8* %0
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store i8 %L, i8* %0
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%E26 = extractelement <2 x i32> %Shuff, i32 1
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%Shuff27 = shufflevector <2 x i32> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> <i32 2, i32 0>
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%I28 = insertelement <16 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, i64 %E12, i32 8
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%B29 = frem double %ZE, 0x235104F0E94F406E
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%Tr = trunc i64 286689 to i8
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%Sl30 = select i1 true, float 0x45B13EA500000000, float %B15
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%Cmp31 = icmp eq i32 %B22, %B22
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br i1 %Cmp31, label %CF74, label %CF80
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CF80: ; preds = %CF74
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%L32 = load i8* %0
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store i8 -1, i8* %0
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%E33 = extractelement <2 x i32> zeroinitializer, i32 1
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%Shuff34 = shufflevector <1 x i64> %Shuff13, <1 x i64> <i64 -1>, <1 x i32> zeroinitializer
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%I35 = insertelement <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 -1, i32 0
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%FC36 = sitofp <1 x i1> %Cmp to <1 x float>
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%Sl37 = select i1 true, <8 x i8> %Shuff20, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%Cmp38 = icmp sgt <2 x i32> %I21, %Shuff27
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%L39 = load i8* %0
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store i8 %Sl24, i8* %0
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%E40 = extractelement <8 x i64> zeroinitializer, i32 1
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%Shuff41 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %Cmp38, <2 x i32> <i32 0, i32 2>
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%I42 = insertelement <4 x i32> zeroinitializer, i32 414573, i32 2
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%B43 = srem i8 %L5, %L39
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%Sl44 = select i1 %Cmp17, i8 %L, i8 %L
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%Cmp45 = fcmp une float 0x3AFCE1A0C0000000, 0.000000e+00
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br i1 %Cmp45, label %CF74, label %CF76
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CF76: ; preds = %CF80
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%L46 = load i8* %0
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store i8 %L39, i8* %0
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%E47 = extractelement <2 x i32> %Shuff27, i32 0
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%Shuff48 = shufflevector <1 x i1> %Sl10, <1 x i1> %Sl10, <1 x i32> <i32 1>
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%I49 = insertelement <1 x i64> <i64 -1>, i64 %E12, i32 0
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%FC50 = fptosi double 0x235104F0E94F406E to i32
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%Sl51 = select i1 %Cmp17, <16 x i64> %I28, <16 x i64> %I28
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%Cmp52 = icmp ne i8 %Tr, %Sl24
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br i1 %Cmp52, label %CF74, label %CF75
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CF75: ; preds = %CF75, %CF76
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%L53 = load i8* %0
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store i8 %L18, i8* %0
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%E54 = extractelement <8 x i8> %Shuff20, i32 5
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%Shuff55 = shufflevector <2 x i32> %Shuff, <2 x i32> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%I56 = insertelement <4 x i32> %I42, i32 %B22, i32 2
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%B57 = sub i64 %E40, %E6
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%Sl58 = select i1 true, i64 303290, i64 %E40
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%Cmp59 = icmp slt i64 %E40, %E6
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br i1 %Cmp59, label %CF75, label %CF78
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CF78: ; preds = %CF75
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%L60 = load i8* %0
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store i8 -69, i8* %0
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%E61 = extractelement <2 x i32> zeroinitializer, i32 0
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%Shuff62 = shufflevector <2 x i32> %Shuff7, <2 x i32> %I21, <2 x i32> <i32 1, i32 3>
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%I63 = insertelement <1 x i1> %Sl16, i1 %Cmp45, i32 0
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%B64 = and i8 %Sl44, -69
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%ZE65 = zext <1 x i1> %Shuff48 to <1 x i64>
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%Sl66 = select i1 true, <1 x i64> %I, <1 x i64> %I49
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%Cmp67 = icmp ugt i64 286689, %E40
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br label %CF
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CF: ; preds = %CF, %CF78
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%L68 = load i8* %0
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store i64 %B57, i64* %2
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%E69 = extractelement <2 x i1> %Shuff41, i32 1
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br i1 %E69, label %CF, label %CF77
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CF77: ; preds = %CF77, %CF
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%Shuff70 = shufflevector <1 x i64> %Shuff34, <1 x i64> <i64 -1>, <1 x i32> zeroinitializer
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%I71 = insertelement <2 x i32> %Shuff, i32 %E26, i32 0
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%Se = sext i8 %L60 to i32
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%Sl72 = select i1 %Cmp45, <2 x i32> %Shuff62, <2 x i32> %I71
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%Cmp73 = fcmp ugt double 0x235104F0E94F406E, 0x235104F0E94F406E
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br i1 %Cmp73, label %CF77, label %CF79
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CF79: ; preds = %CF77
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store i8 %L18, i8* %0
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store i8 %E54, i8* %0
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store i8 %L39, i8* %0
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store i8 %L39, i8* %0
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store i8 %B, i8* %0
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ret void
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}
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