mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
e6562c5088
LowerExpectIntrinsic previously only understood the idiom of an expect intrinsic followed by a comparison with zero. For llvm.expect.i1, the comparison would be stripped by the early-cse pass. Patch by Daniel Micay. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200664 91177308-0d34-0410-b5e6-96231b3b80d8
281 lines
8.1 KiB
LLVM
281 lines
8.1 KiB
LLVM
; RUN: opt -lower-expect -strip-dead-prototypes -S -o - < %s | FileCheck %s
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; CHECK-LABEL: @test1(
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define i32 @test1(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%cmp = icmp sgt i32 %tmp, 1
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%conv = zext i1 %cmp to i32
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%conv1 = sext i32 %conv to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv1, i64 1)
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%tobool = icmp ne i64 %expval, 0
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; CHECK: !prof !0
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; CHECK-NOT: @llvm.expect
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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declare i64 @llvm.expect.i64(i64, i64) nounwind readnone
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declare i32 @f(...)
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; CHECK-LABEL: @test2(
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define i32 @test2(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%conv = sext i32 %tmp to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
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%tobool = icmp ne i64 %expval, 0
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; CHECK: !prof !0
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; CHECK-NOT: @llvm.expect
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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; CHECK-LABEL: @test3(
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define i32 @test3(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%tobool = icmp ne i32 %tmp, 0
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%lnot = xor i1 %tobool, true
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%lnot.ext = zext i1 %lnot to i32
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%conv = sext i32 %lnot.ext to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
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%tobool1 = icmp ne i64 %expval, 0
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; CHECK: !prof !0
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; CHECK-NOT: @llvm.expect
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br i1 %tobool1, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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; CHECK-LABEL: @test4(
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define i32 @test4(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%tobool = icmp ne i32 %tmp, 0
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%lnot = xor i1 %tobool, true
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%lnot1 = xor i1 %lnot, true
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%lnot.ext = zext i1 %lnot1 to i32
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%conv = sext i32 %lnot.ext to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
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%tobool2 = icmp ne i64 %expval, 0
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; CHECK: !prof !0
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; CHECK-NOT: @llvm.expect
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br i1 %tobool2, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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; CHECK-LABEL: @test5(
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define i32 @test5(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%cmp = icmp slt i32 %tmp, 0
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%conv = zext i1 %cmp to i32
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%conv1 = sext i32 %conv to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv1, i64 0)
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%tobool = icmp ne i64 %expval, 0
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; CHECK: !prof !1
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; CHECK-NOT: @llvm.expect
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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; CHECK-LABEL: @test6(
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define i32 @test6(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%conv = sext i32 %tmp to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
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; CHECK: !prof !2
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; CHECK-NOT: @llvm.expect
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switch i64 %expval, label %sw.epilog [
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i64 1, label %sw.bb
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i64 2, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry
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store i32 0, i32* %retval
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br label %return
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sw.epilog: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %sw.epilog, %sw.bb
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%0 = load i32* %retval
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ret i32 %0
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}
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; CHECK-LABEL: @test7(
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define i32 @test7(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%conv = sext i32 %tmp to i64
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%expval = call i64 @llvm.expect.i64(i64 %conv, i64 1)
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; CHECK: !prof !3
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; CHECK-NOT: @llvm.expect
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switch i64 %expval, label %sw.epilog [
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i64 2, label %sw.bb
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i64 3, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry
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%tmp1 = load i32* %x.addr, align 4
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store i32 %tmp1, i32* %retval
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br label %return
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sw.epilog: ; preds = %entry
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store i32 0, i32* %retval
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br label %return
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return: ; preds = %sw.epilog, %sw.bb
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%0 = load i32* %retval
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ret i32 %0
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}
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; CHECK-LABEL: @test8(
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define i32 @test8(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%cmp = icmp sgt i32 %tmp, 1
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%conv = zext i1 %cmp to i32
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%expval = call i32 @llvm.expect.i32(i32 %conv, i32 1)
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%tobool = icmp ne i32 %expval, 0
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; CHECK: !prof !0
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; CHECK-NOT: @llvm.expect
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br i1 %tobool, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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declare i32 @llvm.expect.i32(i32, i32) nounwind readnone
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; CHECK-LABEL: @test9(
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define i32 @test9(i32 %x) nounwind uwtable ssp {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%tmp = load i32* %x.addr, align 4
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%cmp = icmp sgt i32 %tmp, 1
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%expval = call i1 @llvm.expect.i1(i1 %cmp, i1 1)
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; CHECK: !prof !0
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; CHECK-NOT: @llvm.expect
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br i1 %expval, label %if.then, label %if.end
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if.then: ; preds = %entry
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%call = call i32 (...)* @f()
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store i32 %call, i32* %retval
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br label %return
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if.end: ; preds = %entry
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %if.end, %if.then
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%0 = load i32* %retval
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ret i32 %0
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}
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declare i1 @llvm.expect.i1(i1, i1) nounwind readnone
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; CHECK: !0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
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; CHECK: !1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
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; CHECK: !2 = metadata !{metadata !"branch_weights", i32 4, i32 64, i32 4}
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; CHECK: !3 = metadata !{metadata !"branch_weights", i32 64, i32 4, i32 4}
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